Ar724x.cfg
# Atheros AR724x MIPS 24Kc SoC.
# tested on AP99 refererence board
#
# this settings are taken from source of u-boot for this board
# (for PLL) file: u-boot/board/ar7240/common/lowlevel_init.S
# (for DDR) file: u-boot/cpu/mips/ar7240/meminit.c
# with file: u-boot/include/configs/ap99.h
# to execute first part of initialization script
# use this command: ar724x.cpu invoke-event reset-halt-post
adapter_nsrst_delay 100
jtag_ntrst_delay 100
reset_config trst_only separate ;# or use only "reset_config none"
#reset_config none
set CHIPNAME ar724x
jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
set TARGETNAME $CHIPNAME.cpu
target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
$TARGETNAME configure -event reset-halt-post {
#reset Watchdog Timer (when timer ends - resets SoC - then again halted)
mww 0xb806000c 0x400000 ;# rst watchdog timer (delay ~250ms for JTAG adapter with slow speed)
mww 0xb8060008 3 ;# rst watchdog timer control (set control bit in this delay window)
sleep 250 ;# wait resetting SoC (delay for JTAG adapter with fast speed)
poll ;# echo target state cpu (must be: running)
halt
#setup PLL to lowest(default) common denominator 400/400/200 setting
mww 0xb8050000 0x00090828 ;# clr pll mask (rst:02090828)
mww 0xb8050000 0x00050828 ;# CPU:400 DDR:400 AHB:200
mww 0xb8050000 0x00040828 ;# clr pll bypass
#next command will reset for PLL changes to take effect
mww 0xb8050008 2 ;# set reset_switch
mww 0xb8050008 3 ;# set clock_switch (resets SoC)
}
$TARGETNAME configure -event reset-init {
#complete pll initialization
mww 0xb8050008 0 ;# set reset_switch bit & clock_switch bit
# Setup DDR config and flash mapping
mww 0xb8000000 0xc7bc8cd0 ;# DDR cfg cdl val (rst:77be8cd0)
mww 0xb8000004 0x9dd0e6a8 ;# DDR cfg2 cdl val (rst:99d10628)
mww 0xb8000010 8 ;# force precharge all banks
mww 0xb8000008 0x133 ;# DDR mode value init
mww 0xb8000010 1 ;# force EMRS update cycle
mww 0xb800000c 0 ;# clr ext. mode register
mww 0xb8000010 2 ;# force auto refresh all banks
mww 0xb8000010 8 ;# force precharge all banks
mww 0xb8000008 0x33 ;# set DDR mode value CAS=3
mww 0xb8000010 1 ;# force EMRS update cycle
mww 0xb8000014 0x4f10 ;# DDR refresh value
mww 0xb8000018 0xff ;# DDR Read Data This Cycle value (16bit: 0xffff)
mww 0xb800001c 2 ;# delay added to the DQS0 line (normal = 7)
mww 0xb8000020 2 ;# delay added to the DQS1 line (normal = 7)
mww 0xb8000024 0
mww 0xb8000028 0
}
# setup working area somewhere in RAM
$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
# serial SPI capable flash
# flash bank <driver> <base> <size> <chip_width> <bus_width>
Source
http://wiki.openwrt.org/ru/toh/tp-link/tl-mr3420/debrick.using.jtag