File:IWave Systems Technologies Pvt. Ltd..png

From eLinux.org
Jump to: navigation, search
Original file(1,024 × 768 pixels, file size: 84 KB, MIME type: image/png)
Overview

sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards. This IP core provides a relatively simple protocol using maximum available data throughput with a minimum protocol for point-to-point data links. sFPDP links support a wide range of physical interfaces with the most common option being 2.5 gigabits per second multimode fiber.

Highlights • Serial Front Panel Data Port (sFPDP) IP core for FPGA is based on the ANSI/VITA 17.1-2003 standard. The Serial FPDP standard supports three data rates: 1.0625 Gbaud, 2.125 Gbaud, and 2.500 Gbaud.

Benefits • This intellectual property core can be implemented on any transceiver based Xilinx/Altera/Lattice FPGAs.


Features • Compliant with ANSI/VITA 17.1-2003 Serial FPDP standard • Supported link speeds  1.0625 Gbaud  2.125 Gbaud  2.5 Gbaud • Data Frames supported o Unframed Data o Single Frame Data o Fixed Size Repeating Frame Data o Dynamic Size Repeating Frame Data • System Configurations supported o Basic System o Flow Control o Bi-directional Data Flow o Copy Mode o Copy/Loop Mode

Host-Bus interface • Parallel FPDP Configurable parameters • Transmit FIFO depth • Receive FIFO depth • Transmit FIFO watermark to assert SUSPEND output • Transmit FIFO watermark for TX FIFO Overflow signal generation Receive FIFO watermark for STOP/GO signal generation

Target Applications • Digital Signal Processing • Radar ,Sonar ,Range & Telemetry Systems • Instrumentation Recording Systems • High Speed Data Acquisition • Satellite Download • SIGINT – COMINT/ELINT • Medical: Medical Imaging • High Resolution Video • Storage Applications • Digital Receivers • Test Equipments • Spectrum and transient analysis


Deliverables • Design Document • Verilog RTL or Netlist Source code • Test Bench • IP User Guide

FPGA IP Core, 80186 Processor, 80188 Processor, V53A Processor, SDXC, SD / SDIO / MMC Host, SD Memory Slave, SDIO Slave, NAND Flash, ATAPI Host, sFPDP, DMA Controller, PCIe to UART Bridge, PCIe-ISA Bridge,PCI Controller, PCIe to SD-MMC Bridge, SDIO to UART Controller, Memory controller, Video Scaler http://www.iwavesystems.com/product/fpga-ip-cores/interface-cores/serial-fpdp-sfpdp/serial-fpdp-sfpdp.html

File history

Click on a date/time to view the file as it appeared at that time.

Date/TimeThumbnailDimensionsUserComment
current04:14, 7 October 2013Thumbnail for version as of 04:14, 7 October 20131,024 × 768 (84 KB)Iwavesystems (talk | contribs)Overview sFPDP IP Core is based on ANSI/VITA 17.1-2003 Standards. This IP core provides a relatively simple protocol using maximum available data throughput with a minimum protocol for point-to-point data links. sFPDP links support a wide range of phys...
  • You cannot overwrite this file.

There are no pages that link to this file.