Parallella Hardware

Introduction


The key features of the Parallella board are: a Xilinz Zynq SoC which provides a Dual ARM® Cortex™-A9 processor plus programmable logic, 16 or 64-core Epiphany floating-point accelerator (32/100 GFLOPS), high bandwidth expansion via daughter cards, and interfaces that include Gigabit Ethernet, HDMI and MicroSD.

Kickstarter
The initial run of Parallella computers is being funded via a Kickstarter campaign, which on 27th October 2012 had succeeded in raising $898,921 via 4,965 backers, and with those pledging $99 or more receiving at least one board.

Thanks to generous support from Xilinx, the Kickstarter boards will be upgraded to use a Zynq-7020 SoC instead of a Zynq-7010.

General availability
Pre-orders sold out and ordering is currently expected to reopen in January 2013.

Prototype
The first Parallella prototypes shipped in late December 2012 and comprise of a ZedBoard plus a 16 or 64-core Epiphany FMC.

From a software perspective the prototypes are virtually identical to the final form factor boards.

Beta (Gen0)
The first 10 Parallella beta boards came back from assembly on 11th April 2013 and were unveiled four days later at the Linux Foundation Collaboration Summit.

In July 2013 22 Gen0 boards went out Kickstarter backers, and a further 18 to key project contributors.

Backers who were due to receive a board but who opted to wait a little longer will receive a Gen1 board upgraded with a 64-core Epiphany co-processor.

Beta (Gen1)
Gen1 boards were manufactured in August 2013 and these were given to certain backers, key members of the community and some people who won them as prizes at the CodeMesh conference.

Final (Gen1.1)


Fixes include:


 * Fixed HDMI wiring issue
 * Made the USB port host-mode only as default build option
 * Removed flaky mechanical jumper for 5V mounting hole power feed
 * Added more ground vias for improved thermal performance
 * Changed Tantalum caps to ceramic caps to avoid material procurement issues

Specifications
Please note that these are preliminary specifications and subject to change.

Parallella
The Parallella computer is open source hardware: the board design files are published under the Creative Commons Attribution-ShareAlike 3.0 license, and the FPGA HDL sources under the GPL.


 * Preliminary Parallella Gen1 Reference Manual (PDF)
 * Parallella Hardware Design (schematics, board layout, manufacturing files, BOM and 3D models)
 * Parallella Platform Reference Design (ARM-Epiphany interface)

Epiphany
Comprehensive documentation for the Epiphany accelerator has been made available without the need for any special access or NDAs.


 * Epiphany Architecture Reference Manual
 * Epiphany-III 16-core 65nm Microprocessor (E16G301) datasheet
 * Epiphany-IV 64-core 28nm Microprocessor (E64G401) datasheet