PPC405 GP

PowerPC 405GP - CPU Performance 133-266MHz - Features GPIO, PCI, SRAM Memory Controller


 * Datasheet:
 * User's manual|User's Manual
 * Errata:

A fast, flexible solution for embedded developers.

General Description

405GP/GPR Product Photo The AMCC PowerPC 405GP and 405GPr family of 32-bit RISC processors is designed to provide a flexible, fast time-to- market hardware solution to satisfy the demands of high-performance embedded applications. Implemented in the scalable PowerPC architecture, the 405GP and 405GPr processors maintain code compatibility with other PowerPC processors for ease in migration and faster time-to-market. An optimized balance of performance, low power, and features makes them ideal solutions for communication, data storage, and pervasive computing applications.

The 405GP and 405GPr processors support speeds of up to 266MHz and 400MHz respectively. Both incorporate a rich mix of features, such as a PCI interface, an SDRAM Controller, a 64-bit on-chip CoreConnect bus, Ethernet and other on-chip peripheral support, and the IBM CodePack™ code compression engine. In addition, power management features, a small form factor, and low power consumption make the AMCC 405 processor family an ideal platform for applications ranging from networking to video.

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Highlights


 * High-performance, low-power processors for the most demanding embedded applications PowerPC 405GP/405GPr Embedded Processors deliver up to 400MHz performance and a rich mix of features for Internet, communication, data storage, consumer, and imaging applications
 * Includes on-chip SRAM with single-cycle access for faster processing in data-intensive applications, such as routers and switches
 * Supports full application-code compatibility with all other PowerPC® processors for seamless migration
 * Uses the award-winning 64-bit IBM CoreConnect™ high-performance on-chip bus
 * Offers a wide array of small-footprint- package options for high-density applications, such as telecommunications devices
 * Employs the IBM CodePack™ code compression core to reduce system memory requirements and cost

Features


 * On-chip SDRAM Controller
 * Contains separate 32-byte read and 128-byte write buffers
 * Programmable address mapping
 * External Peripheral Controller
 * Supports ROM, EPROM, SRAM
 * Flash and slave peripheral I/O devices
 * 8-, 16-, 32-bit external data bus width
 * Programmable address mapping
 * External Bus Master Controller - Allows external masters to access SDRAM and PCI
 * DMA Controller
 * 4 independent channels
 * Supports transfers between SDRAM, PCI, internal UARTs, and devices on the external peripheral bus
 * PCI Interface
 * 32-bit PCI V2.2 compatible
 * Synchronous and asynchronous operation
 * Internal PCI arbiter supports six PCI masters
 * Supports external arbitration
 * On-chip Ethernet Support
 * 10/100 MAC
 * Dedicated DMA controller
 * CodePack Decompression
 * Stores instructions in memory in compressed format
 * Improves code density by up to 40%
 * Other On-chip Peripherals
 * 2 serial ports
 * Master and slave IIC controller
 * Up to 24 general purpose I/Os
 * Interrupt controller including up to 13 external interrupts