Book E and PPC 440

Difference of Book-E and PPC440 insn

Introduction
This document would make clear differences of Book-E defined instructions and PPC440 implementation to maintain BINUTILS opcode table for Book-E, PPC440 and other Book-E based embedded processors

For this purpose, we don't mention about 64bit operations which PPC440 and most embedded processor don't support. Also we don't mention about differences of registers, like Special Purpose Registers (SPRs).

Section 2 would make clear where Book-E does cover and where it doesn't. Section 3 identifies what Book-E instructions are not supported in PPC440, implementation-dependent operands/ variants. Final section describes PPC440 allocated instructions.

Book-E coverage
In Book-E, PPC Instructions are classified as following;

Book-E defined   - defined and described in Book-E; (Very few instruction may have             implementation-dependent variant              and/or operands) preserved   - for classic PPC use reserved   - for future use allocated   - for implementation-dependent use

E.g.  For PPC440 implementation, Section 5, "Instruction Set", in 440_Programming_Model.pdf shows instruction categories at "Table 4 - PowerPC 440 Instruction Categories".

In general, the Book-E provides for allocated instructions, which are instructions available for implementation-dependent and/or application-specific purposes. Those allocated instructions will be described in processor's manual.

Section 9.1 "Instruction Set Portability", in 440x4_um.pdf, mentions allocated instructions of PPC440 core and "Table 9-2. Allocated Instructions" shows list of the allocated instructions. Due to 440x4_um.pdf, allocated instructions of PPC440 core are not PPC440 specific, common extension for IBM PPC400 embedded series.

Even in the Book-E defined instructions, not in allocated class instructions, there are some implementation-dependent variation. For example, tlbre/tlbwe instructions are defined in the Book-E, may have implementation-dependent operands.

Due to results of searching "implementation-dependent" word from the Book-E instruction set descriptions, Following instructions have implementation-dependent field. In other words, following instructions may have implementation-dependent variants and/or operands.


 * Data Cache Block Touch
 * Data Cache Block Touch for Store
 * Instruction Cache Block Touch
 * TLB Read Entry
 * TLB Search Indexed [Extended]


 * TLB Write Entry

PPC440 limitations
This subsection shows intructions which BOOK-E defines but PPC440 doesn't implement.

"2.3.1 Defined Instruction Class" in 440x4_um.pdf, says PPC440 doesn't support following Book-E defined instructions;

tlbivax[e] mfapidi 64bit operations floating-point operations

The first two instructions and 64bit operations are treated as illegal Instruction. PPC440 core doesn't support floating-point operations inside it, however attached auxiliary processor may support them. Without such auxiliary processor, floating-point operations are treated as illegal instruction.

PPC440 variants
This subsection shows intructions which both BOOK-E and PPC440 defines but PPC440 implement slightly diffrent ways.

Book-E defines following TLB management instructions;

tlbivax[e]   RA,RB    TLB Invalidate Virtual Address Indexed (Extended) tlbre           TLB Read Entry tlbsx[e]   RA,RB    TLB Search Indexed (Extended) tlbsync       TLB Synchronize tlbwe           TLB Write Entry

440x4_um.pdf shows following TLB management instructions.

tlbre       RT, RA, WS    tlbsx[.]    RT, RA, RB    tlbsync tlbwe       RS, RA, WS

Book-E defines following cache block touch instructions;

dcbt[e]       CT,RA,RB    Data Cache Block Touch dcbtst[e]   CT,RA,RB    Data Cache Block Touch for Store icbt[e]       CT,RA,RB    Instruction Cache Block Touch CT means implementation-dependent operand.

However, 440x4_um.pdf says PPC440 have following;

dcbt       RA,RB dcbst       RA,RB icbt       RA,RB

In addition, as a special case, icbt instruction have two opcodes. One is one of allocated opcode (primary:31, secondary:262) for keeping compatibility with previous PPC400 Series. The other is one of Book-E defined opcode (primary:31, secondary:22), because icbt is now part of Book-E.

Allocated Arithmetic
Those instructions support multiply-accumulate, negative multiply-accumulate and multiply halfword.

Multiply-Accumulate
macchw[o][.]         RT,RA,RB macchws[o][.]       RT,RA,RB macchwsu[o][.]   RT,RA,RB macchwu[o][.]    RT,RA,RB machhw[o][.]         RT,RA,RB machhws[o][.]    RT,RA,RB machhwsu[o][.]    RT,RA,RB machhwu[o][.]    RT,RA,RB maclhw[o][.]         RT,RA,RB maclhws[o][.]    RT,RA,RB maclhwsu[o][.]    RT,RA,RB maclhwu[o][.]    RT,RA,RB

Negative Multiply-Accumulate
nmacchw[o][.]    RT,RA,RB nmacchws[o][.]    RT,RA,RB nmachhw[o][.]    RT,RA,RB nmachhws[o][.]    RT,RA,RB nmaclhw[o][.]    RT,RA,RB nmaclhws[o][.]    RT,RA,RB

Multiply-Halfword
mulchw[.]     RT,RA,RB mulchwu[.]     RT,RA,RB mulhhw[.]     RT,RA,RB mulhhwu[.]     RT,RA,RB mullhw[.]     RT,RA,RB mullhwu[.]     RT,RA,RB

Allocated Logical
This instructions detects left-most zero byte, is helpful for implementing function like strlen.

dlmzb[.]   RA,RS,RB

Allocated Cache Management
These instructions flash invalidate entire data/instruction cache array.

dccci       RA,RB iccci       RA,RB

Allocated Cache Debug
These instructions read data/instruction cache

dcread       RT,RA,RB icread       RA,RB

Appendix References
IBM PowerPC(TM) 440 Microprocessor Core Programming Model Overview October 4,2001 PPC440 CPU Core Users Manual SA14-2523-02 July 18, 2002 Book E: Enhanced PowerPC(TM) Architecture Version 1.0 May 7, 2002
 * 440_Programing_Model.pdf
 * 440x4_um.pdf
 * booke_rm.pdf