Index: u-boot-1.1.4/board/omap5912osk/config.mk
===================================================================
--- u-boot-1.1.4.orig/board/omap5912osk/config.mk
+++ u-boot-1.1.4/board/omap5912osk/config.mk
@@ -27,4 +27,8 @@
 #
 
 
-TEXT_BASE = 0x11080000
+# FIXME:
+# This is a quick workaround to not overwrite uboot address
+#
+# TEXT_BASE = 0x11080000
+TEXT_BASE = 0x10880000
Index: u-boot-1.1.4/board/omap5912osk/omap5912osk.c
===================================================================
--- u-boot-1.1.4.orig/board/omap5912osk/omap5912osk.c
+++ u-boot-1.1.4/board/omap5912osk/omap5912osk.c
@@ -37,6 +37,7 @@
 #if defined(CONFIG_OMAP1610)
 #include <./configs/omap1510.h>
 #endif
+#include "omap5912osk.h"
 
 void flash__init (void);
 void ether__init (void);
@@ -290,3 +291,553 @@ void peripheral_power_enable (void)
 
 	*SW_CLOCK_REQUEST |= UART1_48MHZ_ENABLE;
 }
+
+
+/******************************************************
+ Below functions are used for snapshot boot (bootss command)
+*******************************************************/
+
+static inline void wait_loop_countdown(unsigned long n)
+{
+	while (n--)
+	{
+		;
+	}
+}
+
+static inline void enable_clock(void)
+{
+	/* fix errata on omap5910 TIPB */
+	*(short *)(0xfffed308) = 0x0000;
+	*(short *)(0xfffeca08) = 0x0000;
+	*(short *)REG_ARM_SYSST = VAL_ARM_SYSST;
+	wait_loop_countdown(0x400);
+	*(short *)REG_ARM_DPLL1 = VAL_ARM_DPLL1;
+	wait_loop_countdown(0x20);
+	*(short *)REG_ARM_CKCTL = VAL_ARM_CKCTL;
+	wait_loop_countdown(0x20);
+	/* *(short *)REG_ARM_CKCTL &= 0xfff; */
+	*(short *)REG_ARM_RSTCT1 = 0x0;
+	*(short *)REG_ARM_RSTCT2 = 0x1; /* PER_EN bit */
+	*(short *)REG_ARM_IDLECT1 = VAL_ARM_IDLECT1;
+
+	*(short *)REG_ARM_IDLECT2 |= EN_PERCK;
+	*(short *)REG_ARM_IDLECT2 |= EN_XORPCK;
+	*(short *)REG_ARM_IDLECT2 |= EN_TIMCK;
+
+	/* ext clk init */
+	*(short *)COM_CLK_DIV_CTRL_SEL = 0x0000;
+	*(short *)SWD_CLK_DIV_CTRL_SEL = 0x0000;
+
+	/* setup slow interface */
+	*(unsigned long *)REG_EMIFS_CS1 = VAL_EMIFS_CS1;
+	*(unsigned long *)REG_EMIFS_CS3 = VAL_EMIFS_CS3;
+
+#if 1
+	/* linux value */
+	*(short *)REG_ARM_RSTCT1       = VAL_ARM_RSTCT1;
+	*(short *)ULPD_CLOCK_CTRL      = 0x0020;
+#endif
+	wait_loop_countdown(0x800);
+	printf("bootss: changed to clock to 192MHz\n");
+}
+
+static inline void setup_uart(void)
+{
+	*(char *)(UART1_BASE + MDR1_OFFSET) = VAL_MDR1_DISABLE;
+	*(char *)(UART1_BASE + SCR_OFFSET)  = VAL_SCR_TX_WM;
+	*(char *)(UART1_BASE + MDR1_OFFSET) = VAL_MDR1_ENABLE;
+	*(char *)(UART1_BASE + SYSC_OFFSET) = VAL_SYSC;
+
+	*(char *)(UART2_BASE + MDR1_OFFSET) = VAL_MDR1_DISABLE;
+	*(char *)(UART2_BASE + SCR_OFFSET)  = VAL_SCR_TX_WM;
+	*(char *)(UART2_BASE + MDR1_OFFSET) = VAL_MDR1_ENABLE;
+	*(char *)(UART2_BASE + SYSC_OFFSET) = VAL_SYSC;
+
+	*(char *)(UART3_BASE + MDR1_OFFSET) = VAL_MDR1_DISABLE;
+	*(char *)(UART3_BASE + SCR_OFFSET)  = VAL_SCR_TX_WM;
+	*(char *)(UART3_BASE + MDR1_OFFSET) = VAL_MDR1_ENABLE;
+	*(char *)(UART3_BASE + SYSC_OFFSET) = VAL_SYSC;
+}
+
+static inline void setup_osk_irq_config(void)
+{
+	/* borrowed from arch/arm/mach-omap/irq.c linux kernel src */
+	int i, j;
+
+	struct bank {
+		unsigned long base_reg;
+		unsigned long trigger_map;
+	} osk_banks[] ={
+		{.base_reg = 0xfffecb00, .trigger_map = 0xb3fefe8f },
+		{.base_reg = 0xfffe0000, .trigger_map = 0xfdb7c1fd },
+		{.base_reg = 0xfffe0100, .trigger_map = 0xfffff7ff },
+		{.base_reg = 0xfffe0200, .trigger_map = 0xffffffff },
+	};
+#define IRQ_BANK(irq) ((irq) >> 5)
+#define IRQ_BIT(irq)  ((irq) & 0x1f)
+
+	msg_printf("bootss: Total of 128 interrupts in 4 interrupt banks\n");
+
+	/* Mask and clear all interrupts */
+	for (i = 0; i < 4; i++) {
+		unsigned long addr, offset;
+		offset = 0x4;
+		addr = osk_banks[i].base_reg + offset;
+		*(unsigned int *)addr = 0xffffffff;
+		addr = osk_banks[i].base_reg;
+		*(unsigned int *)addr = 0x0;
+	}
+	/* Clear any pending interrupts */
+	{
+		unsigned long addr, offset;
+		offset = 0x18;
+		addr = osk_banks[0].base_reg + offset;
+		*(unsigned int *)addr = 0x3;
+		addr = osk_banks[1].base_reg + offset;
+		*(unsigned int *)addr = 0x3;
+	}
+	/* irq set config */
+	for (i = 0; i < 4; i++) {
+		for (j = i*32; j < (i+1)*32; j++) {
+			unsigned long val, addr, offset;
+			int irq_trigger =
+				osk_banks[i].trigger_map >> IRQ_BIT(j);
+			val = ((irq_trigger & 0x1) << 1);
+			offset = (0x1c) + IRQ_BIT(j)*0x4; /* ILR0 */
+			addr = osk_banks[i].base_reg + offset;
+			*(unsigned int *)addr = val;
+		}
+	}
+	/* unmask level 2 handler */
+	{
+		unsigned long l;
+		l = *((unsigned long *)osk_banks[0].base_reg);
+		l &= ~(0x1);
+		*((unsigned long *)osk_banks[0].base_reg) = l;
+	}
+
+	/* set IH1/2 reg */
+//	*((unsigned long *)(0xfffecb04)) = 0x40000008;
+//	*((unsigned long *)(0xfffe0004)) = 0x00000000;
+	/* set mask of IH1/2 reg */
+//	*((unsigned long *)(0xfffecb04)) = 0x3807bffe;
+//	*((unsigned long *)(0xfffe0004)) = 0xffffbfcd;
+}
+
+static inline void setup_gpio(void)
+{
+	msg_printf("bootss: OMAP GPIO hardware version 1.0\n");
+	/* gpio init */
+//	*(unsigned long *)REG_MPUIO_GPIO_MASKIT = VAL_MPUIO_GPIO_MASKIT;
+	*(unsigned long *)REG_GPIO1_IRQENABLE = VAL_GPIO_IRQENABLE;
+	*(unsigned long *)REG_GPIO1_IRQSTATUS = VAL_GPIO_IRQSTATUS;
+	*(unsigned long *)REG_GPIO2_IRQENABLE = VAL_GPIO_IRQENABLE;
+	*(unsigned long *)REG_GPIO2_IRQSTATUS = VAL_GPIO_IRQSTATUS;
+	*(unsigned long *)REG_GPIO3_IRQENABLE = VAL_GPIO_IRQENABLE;
+	*(unsigned long *)REG_GPIO3_IRQSTATUS = VAL_GPIO_IRQSTATUS;
+	*(unsigned long *)REG_GPIO4_IRQENABLE = VAL_GPIO_IRQENABLE;
+	*(unsigned long *)REG_GPIO4_IRQSTATUS = VAL_GPIO_IRQSTATUS;
+
+	*(unsigned long *)REG_CAM_CLK_CTRL |= 0x04;
+
+	/* osk smc init */
+	*(unsigned long *)REG_GPIO1_EDGE_CTRL1 |= 0x02; /*rising edge*/
+	*(unsigned long *)REG_EMIFS_CS1 |= 0x02;
+
+	/* osk cf init */
+	*(unsigned long *)REG_FUNC_MUX_CTRL10 = VAL_FUNC_MUX_CTRL10;
+	*(unsigned long *)REG_PULLDOWN_CTRL4 = VAL_PULLDOWN_CTRL4;
+	msg_printf("bootss: MUX: initialized M7_1610_GPIO62\n");
+
+	*(unsigned long *)REG_GPIO_EDGE_CTRL2 = VAL_GPIO_EDGE_CTRL2;
+}
+
+static inline void setup_mputimer(void)
+{
+	*(unsigned long *)OMAP_MPU_TIMER1 = MPU_TIMER_CK_ENABLE;
+	*(unsigned long *)OMAP_MPU_TIMER2 = MPU_TIMER_CK_ENABLE;
+	wait_loop_countdown(0x400);
+	*(unsigned long *)(OMAP_MPU_TIMER1 + 4) = 0xffffffff;
+	*(unsigned long *)(OMAP_MPU_TIMER2 + 4) = 0x0000ea5f;
+	wait_loop_countdown(0x400);
+	*(unsigned long *)OMAP_MPU_TIMER1 =
+	  (MPU_TIMER_CK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
+	*(unsigned long *)OMAP_MPU_TIMER2 =
+	  (MPU_TIMER_CK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
+	wait_loop_countdown(0x400);
+
+	printf("bootss: OMAP MPU timers initialized\n");
+}
+
+static inline void setup_dma(void)
+{
+	msg_printf("bootss: OMAP DMA hardware version 1\n"
+	       "\tDMA capabilities: 000c0000:00000000:01ff:003f:007f\n");
+	/* DMA compatible with OMAP 3.2 */
+	*(short *)REG_DMA_MAPPING = VAL_DMA_MAPPING;
+}
+
+static inline void setup_dsp(void)
+{
+	msg_printf("bootss: Initializing OMAP McBSP system\n");
+	*(short *)(0xfffece10) = 0x0004;
+	*(unsigned long *)(0xfffec900) = 0x0000ff1f;
+	*(unsigned long *)(0xfffec900) = 0x0000ff1f;
+	*(unsigned long *)(0xfffecc34) = 0x00000003;
+}
+
+static inline void setup_i2c(void)
+{
+	msg_printf("bootss: OMAP I2C: Driver ver. 1.3\n");
+	*(short *)REG_I2C_SYSC = VAL_I2C_SYSC;
+	*(short *)REG_I2C_PSC  = VAL_I2C_PSC;
+	*(short *)REG_I2C_SCLL = VAL_I2C_SCLL;
+	*(short *)REG_I2C_SCLH = VAL_I2C_SCLH;
+	*(short *)REG_I2C_OA   = VAL_I2C_OA;
+	*(short *)REG_I2C_IE   = VAL_I2C_IE;
+	*(short *)REG_I2C_CON  = VAL_I2C_CON;
+}
+
+static inline void setup_tps65010(void)
+{
+	msg_printf("bootss: tps65010: version 20 Jan 2005\n");
+	/* tons of omap_i2c_isr... (currently neglecting) */
+
+	*(unsigned long *)REG_MPUIO_IO_CTRL = VAL_MPUIO_IO_CTRL;
+	*(unsigned long *)REG_MPUIO_INT_EDGE = VAL_MPUIO_INT_EDGE;
+//	*(unsigned long *)REG_MPUIO_GPIO_MASKIT = VAL_MPUIO_GPIO_MASKIT;
+
+	/* tons of omap_i2c_isr... (currently neglecting) */
+}
+
+static inline void setup_uwire_cs0(void)
+{
+	*(short *)REG_UWIRE_SETUP3 = VAL_UWIRE_SETUP3;
+	*(unsigned long *)REG_FUNC_MUX_CTRL8 = VAL_FUNC_MUX_CTRL8;
+	*(unsigned long *)REG_PULLDOWN_CTRL1 = 0x00200000;
+	msg_printf("bootss: MUX: initialized N14_1610_UWIRE_CS0\n");
+}
+
+static inline void setup_uwire_cs1(void)
+{
+	*(unsigned long *)REG_FUNC_MUX_CTRL7 = 0x00080000;
+	*(unsigned long *)REG_PULLDOWN_CTRL1 = 0x00204000;
+	msg_printf("bootss: MUX: initialized N15_1610_UWIRE_CS1\n");
+}
+
+static inline void setup_ocpi(void)
+{
+	/* clear OCPI protection */
+	*(unsigned long *)REG_OCPI_PROTECT = VAL_OCPI_PROTECT;
+	*(unsigned long *)REG_SECURE_MODE = VAL_SECURE_MODE;
+	msg_printf("bootss: OMAP OCPI interconnect driver loaded\n");
+}
+
+static inline void setup_pm(void)
+{
+	msg_printf("bootss: Power Management for TI OMAP.\n");
+	/* ifndef CONFIG_USB */
+#if 0
+/* maybe need to do this?
+   omap_writel(0x00000000, 0xfffe0408) at omap_pm_init
+   omap_writel(0x0000e000, 0xfffe0404) at omap_pm_init *
+   omap_writew(0x00000020, 0xfffe0830) at omap_pm_init *
+   omap_writew(0x00000200, 0xfffe0834) at omap_pm_init *
+*/
+#endif
+//	*(short *)REG_ARM_IDLECT3 = VAL_ARM_IDLECT3;
+	*(unsigned long *)REG_FUNC_MUX_CTRL7 = VAL_FUNC_MUX_CTRL7;
+	msg_printf("bootss: MUX: initialized T20_1610_LOW_PWR\n");
+}
+
+static inline void setup_lcd_controller(short *sp)
+{
+	int i;
+	short *sp0 = sp;
+	for (i = 0; i < 0x22; i++, sp++)
+	{
+		*sp = 0x0000;
+	}
+	sp0++; *sp0 = 0x0400;
+	sp0--;
+	*sp0 = 0x0040; *sp0 = 0x00c0; *sp0 = 0x20c0; *sp0 = 0x60c0;
+}
+
+static inline void setup_lcd(void)
+{
+	/* initialize omap lcd control */
+	*(unsigned long *)REG_LCDC_CONTROL = VAL_LCDC_CONTROL;
+	/* change LCD div (clock speed) */
+	*(short *)REG_ARM_CKCTL = 0x0507;
+//	*(short *)REG_ARM_IDLECT2 = VAL_ARM_IDLECT2;
+	msg_printf("bootss: OMAP LCD controller initialized.\n");
+//	setup_lcd_controller((short *)0xfffed800);
+//	setup_lcd_controller((short *)0xfffed840);
+}
+
+static inline void setup_pwl(void)
+{
+	/* set dma priority */
+	*(unsigned long *)REG_DMA_PRIORITY = VAL_DMA_PRIORITY;
+	*(unsigned long *)REG_FUNC_MUX_CTRL6 = VAL_FUNC_MUX_CTRL6;
+	*(unsigned long *)REG_PULLDOWN_CTRL0 = VAL_PULLDOWN_CTRL0;
+	msg_printf("bootss: MUX: initialized PWL\n");
+}
+
+static inline void setup_osk_panel(void)
+{
+	/* enable PWL unit */
+	*(char *)REG_OMAP16XX_PWL_CLK = VAL_OMAP16XX_PWL_CLK;
+	*(char *)REG_OMAP16XX_PWL = VAL_OMAP16XX_PWL;
+	/* GPIO1 as output */
+	*(unsigned long *)REG_GPIO1_DIRECTION = VAL_GPIO1_DIRECTION;
+	*(unsigned long *)REG_GPIO1_SET_DATAOUT = VAL_GPIO1_SET_DATAOUT;
+
+	return;
+#if 0
+
+	/* setup OMAP LCDC */
+	*(unsigned long *)(0xfffec000) = 0xfe000080;
+	*(unsigned long *)(0xfffec00c) = 0xfc000000;
+	*(unsigned long *)(0xfffec004) = 0x47279cef;
+	*(unsigned long *)(0xfffec008) = 0x0001013f;
+	*(unsigned long *)(0xfffec00c) = 0xfc00000c;
+
+	*(unsigned long *)(0xfffec000) = 0xfe100080;
+	*(unsigned long *)(0xfffec000) = 0xfe100088;
+	*(unsigned long *)(0xfffec010) = 0xffffff80;
+	*(unsigned long *)(0xfffec000) = 0xfe100099;
+
+	*(unsigned long *)(0xfffec000) = 0xfe200088;
+	*(unsigned long *)(0xfffec000) = 0xfe200089;
+	*(unsigned long *)(0xfffec000) = 0xfe200088;
+	*(unsigned long *)(0xfffec000) = 0xfe200080;
+	*(unsigned long *)(0xfffec010) = 0xffffff81;
+
+	*(unsigned long *)(0xfffec010) = 0xffffff80;
+	*(unsigned long *)(0xfffec000) = 0xfe200089;
+
+	/* lcd dma ... currently neglecting... */
+#endif
+}
+
+static inline void enable_smc91x(void)
+{
+	/* enable clock */
+	*(unsigned long *)REG_CAM_CLK_CTRL |= 0x04;
+	wait_loop_countdown(0x100);
+	/* init setup */
+#if 0
+	*(unsigned long *)REG_GPIO1_EDGE_CTRL1 |= 0x02; /*rising edge*/
+	wait_loop_countdown(0x100);
+	*(unsigned long *)REG_EMIFS_CS1 |= 0x02;  /*wait state errfix*/
+	wait_loop_countdown(0x100);
+#endif
+#if 1
+	/*reset smc91*/
+	*(short *)REG_SELECT_BANK = 0x0002;
+	*(short *)REG_INT_MASK    = 0x0000;
+
+	*(short *)REG_SELECT_BANK = 0x0000;
+	*(short *)REG_RCR = 0x8000;
+
+	*(short *)REG_SELECT_BANK = 0x0001;
+	*(short *)REG_CONFIG = 0x9000;
+
+	udelay(1);
+
+	*(short *)REG_SELECT_BANK = 0x0000;
+	*(short *)REG_RCR = 0x0000;
+	*(short *)REG_TCR = 0x0000;
+
+	*(short *)REG_SELECT_BANK = 0x0001;
+	*(short *)REG_CONTROL |= 0x0080;
+	*(short *)REG_CONTROL |= 0x0800;
+
+	*(short *)REG_SELECT_BANK = 0x0002;
+	*(short *)REG_MMU_CMD = (2<<5);
+	while (*(short *)REG_MMU_CMD & 0x0001)
+		; /* wait mmu busy */
+
+	/*enable smc91*/
+	*(short *)REG_SELECT_BANK = 0x0000;
+	*(short *)REG_TCR = 0x0481;
+	*(short *)REG_RCR = 0x0300;
+
+	*(short *)REG_SELECT_BANK = 0x0002;
+	*(short *)REG_INT_MASK = 0x31<<8;
+#endif
+#if 0
+	/* set to linux */
+	*(short *)REG_SELECT_BANK = 0x0001;
+	*(short *)REG_CONFIG = 0x30b1;
+	*(short *)REG_SELECT_BANK = 0x0002;
+	*(short *)REG_INT_MASK = 0x338d;
+#endif
+}
+
+static inline void setup_nor_cs3(void)
+{
+
+	/* 0xc2880000 --> 0x00000000 */
+	*(short *)(0x00000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000000) = 0x00ff;
+	wait_loop_countdown(0x100);
+	*(short *)(0x000000aa) = 0x0098;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000aaa) = 0x00aa;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000554) = 0x0055;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000aaa) = 0x0090;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000000) = 0x00ff;
+	wait_loop_countdown(0x100);
+/* omap_nor_cs3: Found 1 x16 devices at 0x0 in 16-bit bank */
+
+	/* 0xc3880000 --> 0x01000000 */
+	wait_loop_countdown(0x100);
+	*(short *)(0x01000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x01000000) = 0x00ff;
+	wait_loop_countdown(0x100);
+	*(short *)(0x010000aa) = 0x0098;
+	wait_loop_countdown(0x100);
+	*(short *)(0x01000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x01000000) = 0x00ff;
+	wait_loop_countdown(0x100);
+/* omap_nor_cs3: Found 1 x16 devices at 0x1000000 in 16-bit bank */
+
+	/* 0xc48800000 --> 0x02000000 */
+	wait_loop_countdown(0x100);
+	*(short *)(0x02000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x02000000) = 0x00ff;
+	wait_loop_countdown(0x100);
+	*(short *)(0x020000aa) = 0x0098;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000000) = 0x00ff;
+	wait_loop_countdown(0x100);
+	/* 0xc5880000 --> 0x03000000 */
+	wait_loop_countdown(0x100);
+	*(short *)(0x03000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x03000000) = 0x00ff;
+	wait_loop_countdown(0x100);
+	*(short *)(0x030000aa) = 0x0098;
+	wait_loop_countdown(0x100);
+	*(short *)(0x01000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x01000000) = 0x00ff;
+	wait_loop_countdown(0x100);
+/* Intel/Sharp Extended Query Table at 0x0031 */
+	wait_loop_countdown(0x100);
+	*(short *)(0x000000aa) = 0x0098;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000000) = 0x00f0;
+	wait_loop_countdown(0x100);
+	*(short *)(0x00000000) = 0x00ff;
+	wait_loop_countdown(0x100);
+
+/*
+Using buffer write method
+    cfi_cmdset_0001: Erase suspend on write enabled
+    Creating 4 MTD partitions on "omap_nor_cs3":
+      0x00000000-0x00020000 : "bootloader"
+      0x00020000-0x00040000 : "params"
+      0x00040000-0x00240000 : "kernel"
+      0x00240000-0x02000000 : "filesystem"
+*/
+}
+
+static inline void setup_kp(void)
+{
+#if 0
+	msg_printf("bootss: OMAP Keypad Driver\n");
+	*(short *)REG_MPUIO_KBD_MASKIT = 0x0001;
+	*(short *)(0xfffb5014) = 0x00ff;	udelay(10);
+	*(short *)(0xfffb5014) = 0x00fe;	udelay(10);
+	*(short *)(0xfffb5014) = 0x00fd;	udelay(10);
+	*(short *)(0xfffb5014) = 0x00fb;	udelay(10);
+	*(short *)(0xfffb5014) = 0x00f7;	udelay(10);
+	*(short *)(0xfffb5014) = 0x00ef;	udelay(10);
+	*(short *)(0xfffb5014) = 0x00df;	udelay(10);
+	*(short *)(0xfffb5014) = 0x00bf;	udelay(10);
+	*(short *)(0xfffb5014) = 0x007f;	udelay(10);
+	*(short *)(0xfffb5014) = 0x0000;	udelay(10);
+	*(short *)REG_MPUIO_KBD_MASKIT = 0x0000;
+#endif
+
+	*(unsigned long *)REG_FUNC_MUX_CTRL6 = VAL_FUNC_MUX_CTRL6;
+	*(unsigned long *)REG_PULLDOWN_CTRL1 = VAL_PULLDOWN_CTRL1;
+	msg_printf("bootss: MUX: initialized P20_1610_GPIO4\n");
+
+	*(unsigned long *)REG_GPIO1_DIRECTION = VAL_GPIO1_DIRECTION;
+	*(unsigned long *)REG_GPIO1_EDGE_CTRL1 = VAL_GPIO1_EDGE_CTRL1;
+	*(short *)REG_UWIRE_SETUP1 = VAL_UWIRE_SETUP1;
+	*(unsigned long *)REG_GPIO1_SETIRQENABLE1 = 0x00000010;
+	msg_printf("bootss: OMAP touchscreen driver initialized\n");
+}
+
+static inline void setup_linux(void)
+{
+	*(unsigned long *)REG_FUNC_MUX_CTRL10 = VAL_FUNC_MUX_CTRL10; //gpio
+	*(unsigned long *)REG_PULLDOWN_CTRL4 = VAL_PULLDOWN_CTRL4; //gpio
+
+	*(short *)REG_UWIRE_SETUP3 = VAL_UWIRE_SETUP3;
+	*(short *)REG_ARM_IDLECT3 = VAL_ARM_IDLECT3; //@pm
+	*(unsigned long *)REG_FUNC_MUX_CTRL7 = VAL_FUNC_MUX_CTRL7; //@pm
+	*(short *)REG_ARM_CKCTL = 0x0507; //@lcd
+	*(short *)REG_ARM_IDLECT2 = VAL_ARM_IDLECT2; //@lcd
+
+	*(unsigned long *)REG_FUNC_MUX_CTRL6 = VAL_FUNC_MUX_CTRL6; //@kp
+	*(unsigned long *)REG_PULLDOWN_CTRL1 = VAL_PULLDOWN_CTRL1; //@kp
+	*(unsigned long *)REG_GPIO1_DIRECTION  = VAL_GPIO1_DIRECTION;  //@kp
+	*(unsigned long *)REG_GPIO1_EDGE_CTRL1 = VAL_GPIO1_EDGE_CTRL1; //@kp
+
+	*(unsigned long *)REG_GPIO1_IRQENABLE1 = VAL_GPIO1_IRQENABLE1;
+	*(unsigned long *)REG_GPIO1_INTSTATUS2 = VAL_GPIO1_INTSTATUS2;
+	*(unsigned long *)REG_MPUIO_GPIO_MASKIT = VAL_MPUIO_GPIO_MASKIT; //tps
+}
+
+void ss_pre_setup_peripherals(void)
+{
+	enable_clock();
+	setup_uart();
+	setup_osk_irq_config();
+	setup_gpio();
+	setup_mputimer();
+	setup_dma();
+	setup_dsp();
+	setup_i2c();
+	setup_tps65010();
+	setup_uwire_cs0();
+	setup_uwire_cs1();
+	setup_ocpi();
+	setup_pm();
+	setup_lcd();
+	setup_pwl();
+	setup_osk_panel();
+//	enable_smc91x();
+	setup_nor_cs3();
+	setup_kp();
+	setup_linux();
+}
+
+void ss_post_setup_peripherals(void)
+{
+	/* FIXME: debug, set cs3 nor to erase mode...
+	 * Without this workaround, mtd flash would malfunction in
+	 * linux kernel.
+	 */
+	*(short *)(0x00240000) = 0x0020; // BLOCK ERASE CMD
+}
Index: u-boot-1.1.4/board/omap5912osk/omap5912osk.h
===================================================================
--- /dev/null
+++ u-boot-1.1.4/board/omap5912osk/omap5912osk.h
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2006
+ *     Sony Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __OMAP5912OSK_H
+#define __OMAP5912OSK_H
+
+	/* register address */
+#define CLKGEN_REG_BASE         (0xfffece00)
+#define REG_ARM_CKCTL           (CLKGEN_REG_BASE + 0x00)
+#define REG_ARM_IDLECT1         (CLKGEN_REG_BASE + 0x04)
+#define REG_ARM_IDLECT2         (CLKGEN_REG_BASE + 0x08)
+#define REG_ARM_EWUPCT          (CLKGEN_REG_BASE + 0x0C)
+#define REG_ARM_RSTCT1          (CLKGEN_REG_BASE + 0x10)
+#define REG_ARM_RSTCT2          (CLKGEN_REG_BASE + 0x14)
+#define REG_ARM_SYSST           (CLKGEN_REG_BASE + 0x18)
+#define REG_ARM_IDLECT3         (CLKGEN_REG_BASE + 0x24)
+#define REG_ARM_DPLL1           (0xfffecf00)
+#define COM_CLK_DIV_CTRL_SEL    (0xfffe0878)
+#define MOD_CONF_CTRL_0         (0xfffe1080)
+#define MOD_CONF_CTRL_1         (0xfffe1110)
+#define SWD_CLK_DIV_CTRL_SEL    (0xfffe0874)
+#define ULPD_CLOCK_CTRL         (0xfffe0830)
+	/* register set value */
+#define VAL_ARM_SYSST           (0x1000)
+#define VAL_ARM_DPLL1           (0x2810)
+#define VAL_ARM_CKCTL           (0x050f)
+#define VAL_ARM_RSTCT1          (0x0004)
+#define VAL_ARM_IDLECT1         (0x0400)
+#define VAL_ARM_IDLECT2         (0x008e) /*(0x0000)*/
+#define VAL_ARM_IDLECT3         (0x003f) /*(0x0000)*/
+	/* ARM_IDLECT2 bit shifts */
+#define EN_WDTCK        0
+#define EN_XORPCK       1
+#define EN_PERCK        2
+#define EN_LCDCK        3
+#define EN_LBCK         4 /* Not on 1610/1710 */
+/*#define EN_HSABCK     5*/
+#define EN_APICK        6
+#define EN_TIMCK        7
+
+/* MPU TIMER */
+#define OMAP_MPU_TIMER1         (0xfffec500)
+#define OMAP_MPU_TIMER2         (0xfffec600)
+#define OMAP_MPU_TIMER3         (0xfffec700)
+#define MPU_TIMER_FREE          (1 << 6)
+#define MPU_TIMER_CK_ENABLE     (1 << 5)
+#define MPU_TIMER_AR            (1 << 1)
+#define MPU_TIMER_ST            (1 << 0)
+
+/* EMIFS */
+#define REG_EMIFS_CS0           (0xfffecc10)
+#define REG_EMIFS_CS1           (0xfffecc14)
+#define REG_EMIFS_CS3           (0xfffecc1c)
+#define VAL_EMIFS_CS0           (0x002130b0)
+#define VAL_EMIFS_CS1           (0x00001133)
+#define VAL_EMIFS_CS3           (0x88013141)
+
+/* MPUIO */
+#define REG_MPUIO_IO_CTRL       (0xfffb5008)
+#define VAL_MPUIO_IO_CTRL       (0x0000ffff)
+#define REG_MPUIO_INT_EDGE      (0xfffb501c)
+#define VAL_MPUIO_INT_EDGE      (0x00000000)
+#define REG_MPUIO_KBD_MASKIT    (0xfffb5028)
+#define REG_MPUIO_GPIO_MASKIT   (0xfffb502c)
+
+/* GPIO1 */
+#define REG_GPIO1_IRQENABLE     (0xfffbe41c)
+#define REG_GPIO1_IRQENABLE1    (0xfffbe41c)
+#define REG_GPIO2_IRQENABLE     (0xfffbec1c)
+#define REG_GPIO3_IRQENABLE     (0xfffbb41c)
+#define REG_GPIO4_IRQENABLE     (0xfffbbc1c)
+
+#define REG_GPIO1_IRQSTATUS     (0xfffbe418)
+#define REG_GPIO2_IRQSTATUS     (0xfffbec18)
+#define REG_GPIO3_IRQSTATUS     (0xfffbb418)
+#define REG_GPIO4_IRQSTATUS     (0xfffbbc18)
+
+#define REG_GPIO1_INTSTATUS2    (0xfffbe420)
+
+#define REG_GPIO1_DIRECTION     (0xfffbe434)
+#define REG_GPIO2_DIRECTION     (0xfffbec34)
+#define REG_GPIO3_DIRECTION     (0xfffbb434)
+#define REG_GPIO4_DIRECTION     (0xfffbbc34)
+#define REG_GPIO_EDGE_CTRL2     (0xfffbbc3c)
+#define VAL_GPIO_EDGE_CTRL2     (0x00001000)
+
+#define REG_GPIO1_SETIRQENABLE1 (0xfffbe4dc)
+#define REG_GPIO2_SETIRQENABLE1 (0xfffbecdc)
+#define REG_GPIO3_SETIRQENABLE1 (0xfffbb4dc)
+#define REG_GPIO4_SETIRQENABLE1 (0xfffbbcdc)
+
+#define REG_GPIO1_EDGE_CTRL1    (0xfffbe438)
+#define REG_CAM_CLK_CTRL        (0xfffe087c)
+
+#define REG_GPIO1_SET_DATAOUT   (0xfffbe4f0)
+#define VAL_GPIO1_SET_DATAOUT   (0x00000004)
+
+#define VAL_MPUIO_GPIO_MASKIT   (0xfffd)
+#define VAL_GPIO_IRQENABLE      (0x0000)
+#define VAL_GPIO_IRQSTATUS      (0xffff)
+
+/* linux setup values */
+#define VAL_GPIO1_IRQENABLE1    (0x00000011)
+#define VAL_GPIO1_INTSTATUS2    (0x00000011)
+#define VAL_GPIO1_DIRECTION     (0x0000fffb)
+#define VAL_GPIO2_DIRECTION     (0x0000ffff)
+#define VAL_GPIO3_DIRECTION     (0x0000ffff)
+#define VAL_GPIO4_DIRECTION     (0x0000ffff)
+#define VAL_GPIO1_EDGE_CTRL1    (0x00000102)
+#define VAL_GPIO1_SETIRQENABLE1 (0x00000011)
+#define VAL_GPIO2_SETIRQENABLE1 (0x00000000)
+#define VAL_GPIO3_SETIRQENABLE1 (0x00000000)
+#define VAL_GPIO4_SETIRQENABLE1 (0x00000000)
+
+#define OMAP_OSK_ETHR_START     (0x04800300)
+#define REG_SELECT_BANK         (0x0480030e)
+#define REG_TCR                 (0x04800300) /*bank 0*/
+#define REG_RCR                 (0x04800304) /*bank 0*/
+#define REG_CONTROL             (0x0480030c)
+#define REG_CONFIG              (0x04800300) /*bank 1*/
+#define REG_MMU_CMD             (0x04800300) /*bank 2*/
+#define REG_INT_MASK            (0x0480030c) /*bank 2*/
+
+#define REG_PULLDOWN_CTRL0      (0xfffe1040)
+#define VAL_PULLDOWN_CTRL0      (0x00000000)
+#define REG_PULLDOWN_CTRL1      (0xfffe1044)
+#define VAL_PULLDOWN_CTRL1      (0x00204080)
+#define REG_PULLDOWN_CTRL4      (0xfffe10ac)
+#define VAL_PULLDOWN_CTRL4      (0x01000000)
+#define REG_FUNC_MUX_CTRL6      (0xfffe101c)
+#define VAL_FUNC_MUX_CTRL6      (0x00000009)
+#define REG_FUNC_MUX_CTRL7      (0xfffe1020)
+#define VAL_FUNC_MUX_CTRL7      (0x00081000)
+#define REG_FUNC_MUX_CTRL8      (0xfffe1024)
+#define VAL_FUNC_MUX_CTRL8      (0x00001200)
+#define REG_FUNC_MUX_CTRL10     (0xfffe1098)
+#define VAL_FUNC_MUX_CTRL10     (0x00000000)
+#define REG_DMA_MAPPING         (0xfffedc04)
+#define VAL_DMA_MAPPING         (0x00000008)
+#define REG_OCPI_PROTECT        (0xfffec334)
+#define VAL_OCPI_PROTECT        (0x00000000)
+#define REG_SECURE_MODE         (0xfffec338)
+#define VAL_SECURE_MODE         (0x00000000)
+#define REG_LCDC_CONTROL        (0xfffec000)
+#define VAL_LCDC_CONTROL        (0x00000000)
+#define REG_DMA_PRIORITY        (0xfffecc08)
+#define VAL_DMA_PRIORITY        (0x00000f00)
+
+#define UART1_BASE              (0xfffb0000)
+#define UART2_BASE              (0xfffb0800)
+#define UART3_BASE              (0xfffb9800)
+#define MDR1_OFFSET             (0x00000020)
+#define SCR_OFFSET              (0x00000040)
+#define SYSC_OFFSET             (0x00000054)
+#define VAL_MDR1_DISABLE        (0x07)
+#define VAL_SCR_TX_WM           (0x08)
+#define VAL_MDR1_ENABLE         (0x00)
+#define VAL_SYSC                (0x01)
+
+/* I2C */
+#define REG_I2C_BASE            (0xfffb3800)
+#define REG_I2C_SYSC            (REG_I2C_BASE + 0x20)
+#define REG_I2C_PSC             (REG_I2C_BASE + 0x30)
+#define REG_I2C_SCLL            (REG_I2C_BASE + 0x34)
+#define REG_I2C_SCLH            (REG_I2C_BASE + 0x38)
+#define REG_I2C_OA              (REG_I2C_BASE + 0x28)
+#define REG_I2C_IE              (REG_I2C_BASE + 0x04)
+#define REG_I2C_CON             (REG_I2C_BASE + 0x24)
+#define VAL_I2C_SYSC            (0x0002)
+#define VAL_I2C_PSC             (0x0000)
+#define VAL_I2C_SCLL            (0x0035)
+#define VAL_I2C_SCLH            (0x0035)
+#define VAL_I2C_OA              (0x0001)
+#define VAL_I2C_IE              (0x001f)
+#define VAL_I2C_CON             (0x8000)
+
+#define REG_UWIRE_SETUP1        (0xfffb3008)
+#define VAL_UWIRE_SETUP1        (0xf803)
+#define REG_UWIRE_SETUP3        (0xfffb3010)
+#define VAL_UWIRE_SETUP3        (0x0001)
+
+#define REG_OMAP16XX_PWL        (0xfffb5800)
+#define VAL_OMAP16XX_PWL        (0xff)
+#define REG_OMAP16XX_PWL_CLK    (0xfffb5804)
+#define VAL_OMAP16XX_PWL_CLK    (0x01)
+
+//#define msg_printf(fmt, arg...) printf(fmt,##arg)
+#define msg_printf(fmt, arg...) do{}while(0)
+
+#endif __OMAP5912OSK_H