`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: David Carne // // Create Date: 22:03:12 04/12/2006 // Design Name: // Module Name: freq_count // Project Name: // Target Devices: // Tool versions: // Description: generic frequency counter // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module freq_count(clk_50m, samp_clk, freq); input clk_50m; input samp_clk; output reg [31:0] freq = 0; reg [31:0] onesec_div = 0; reg [31:0] freq_cnt = 0; reg clear_bit = 0; reg clear_sync = 0; always @(posedge samp_clk) begin if (clear_bit != clear_sync) begin freq_cnt <= 0; clear_sync <= clear_bit; end else freq_cnt <= freq_cnt + 1; end always @(posedge clk_50m) begin if (onesec_div >= 32'd50000000) begin freq <= freq_cnt; clear_bit <= !clear_bit; onesec_div <= 0; end else onesec_div <= onesec_div + 1; end endmodule