BeagleBoardOpenOCD - Revision history

Wmat: fixing more broken indenting

2012-08-12T18:07:47Z

fixing more broken indenting

Wmat: fixing broken indent

2012-08-12T18:06:04Z

fixing broken indent

Wmat: categorizing as an openocd page

2012-04-26T23:41:05Z

categorizing as an openocd page

Wmat: typo

2011-07-05T03:03:41Z

typo

Peter Huewe: Fix a wiki link

2011-04-13T22:01:15Z

Fix a wiki link

Fcarpen at 03:02, 4 August 2010

2010-08-04T03:02:53Z

Fcarpen at 22:45, 1 August 2010

2010-08-01T22:45:34Z

Rickbronson: /* Example session */

2010-05-11T16:31:01Z

‎Example session

Dirk: Fix formatting errors

2010-04-02T09:43:30Z

Fix formatting errors

Dirk: Update example session

2010-04-02T09:42:38Z

Update example session

@@ Line 323: / Line 323: @@
 omap3530.jrc           Y     0x0b7ae02f 0x0b7ae02f     6 0x01  0x3f
- > '''resume'''
+> '''resume'''
- > '''poll'''
+> '''poll'''
   background polling: on
   TAP: omap3530.dap (enabled)
   target state: running
- > '''halt'''
+> '''halt'''
   target state: halted
   target halted in ARM state due to debug-request, current mode: Supervisor
@@ Line 336: / Line 336: @@
   MMU: disabled, D-Cache: disabled, I-Cache: enabled
- > '''poll'''
+> '''poll'''
   background polling: on
   TAP: omap3530.dap (enabled)
@@ Line 344: / Line 344: @@
   MMU: disabled, D-Cache: disabled, I-Cache: enabled
- > '''reg'''
+> '''reg'''
   ===== ARM registers
   (0) r0 (/32): 0x49020000 (dirty)
@@ Line 387: / Line 387: @@
   (39) spsr_mon (/32)
- > '''resume'''
+> '''resume'''
- > '''poll'''
+> '''poll'''
   background polling: on
   TAP: omap3530.dap (enabled)
   target state: running
- > '''soft_reset_halt'''
+> '''soft_reset_halt'''
   requesting target halt and executing a soft reset
   Target omap3.cpu does not support soft_reset_halt
- > '''cortex_a8 cache_info'''
+> '''cortex_a8 cache_info'''
   cache type: 0x0, unified cache
   D-Cache: linelen 8, associativity 2, nsets 64, cachesize 0x400
   I-Cache: linelen 8, associativity 2, nsets 64, cachesize 0x400
- > '''halt'''
+> '''halt'''
   target state: halted
   target halted in ARM state due to debug-request, current mode: Supervisor
@@ Line 409: / Line 409: @@
   MMU: disabled, D-Cache: disabled, I-Cache: enabled
- > '''arm disassemble 0x80e88158 10'''
+> '''arm disassemble 0x80e88158 10'''
 x80e88158      0xe3130001      TST r3, #0x1
 x80e8815c      0x0afffffc      BEQ 0x80e88154
@@ Line 421: / Line 421: @@
 x80e8817c      0xe59f0000      LDR r0, [r15]
- > '''step'''
+> '''step'''
   target state: halted
   target halted in ARM state due to breakpoint, current mode: Supervisor
@@ Line 427: / Line 427: @@
   MMU: disabled, D-Cache: disabled, I-Cache: enabled
- > '''step'''
+> '''step'''
   target state: halted
   target halted in ARM state due to breakpoint, current mode: Supervisor
@@ Line 433: / Line 433: @@
   MMU: disabled, D-Cache: disabled, I-Cache: enabled
- > '''bp 0x80e88160 4 hw'''
+> '''bp 0x80e88160 4 hw'''
   breakpoint set at 0x80e88160
- > '''resume'''
+> '''resume'''
   ''... type anything in U-Boot until breakpoint is hit ...''
@@ Line 445: / Line 445: @@
   MMU: disabled, D-Cache: disabled, I-Cache: enabled
- > '''bp'''
+> '''bp'''
 x80e88160, 0x4, 1
- > '''rbp 0x80e88160'''
+> '''rbp 0x80e88160'''
- > '''resume'''
+> '''resume'''
 =GDB ARM=

@@ Line 316: / Line 316: @@
   MMU: disabled, D-Cache: disabled, I-Cache: enabled
- > '''scan_chain'''
+> '''scan_chain'''
      TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
   -- ------------------- -------- ---------- ---------- ----- ----- ------

← Older revision		Revision as of 23:41, 26 April 2012
Line 873:		Line 873:

	These are the component identification registers. See table 12-51 of [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344h/DDI0344H_cortex_a8_r3p0_trm.pdf Cortex-A8 TRM].		These are the component identification registers. See table 12-51 of [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344h/DDI0344H_cortex_a8_r3p0_trm.pdf Cortex-A8 TRM].
		+
		+	[[Category:OpenOCD]]

@@ Line 33: / Line 33: @@
   > git clone git://openocd.git.sourceforge.net/gitroot/openocd/openocd openocd
-For Flyswatter you additionally need [http://www.ftdichip.com/Drivers/D2XX.htm libftd2xx] or [http://www.intra2net.com/de/produkte/opensource/ftdi/ libFTDI]. While libFTDI is available in source, libftd2xx is supposed to be 50% [http://www.beagleboard.org/irclogs/index.php?date=2008-10-16#T16:06:22 faster] than libFTDI. The libtfd2xx binaries are available booth as shared library or linkable archive.
+For Flyswatter you additionally need [http://www.ftdichip.com/Drivers/D2XX.htm libftd2xx] or [http://www.intra2net.com/de/produkte/opensource/ftdi/ libFTDI]. While libFTDI is available in source, libftd2xx is supposed to be 50% [http://www.beagleboard.org/irclogs/index.php?date=2008-10-16#T16:06:22 faster] than libFTDI. The libtfd2xx binaries are available both as shared library or linkable archive.
 If you downloaded OpenOCD git and have libftd2xx or libFTDI, build OpenOCD (assuming you extracted/built FTDI library already):

@@ Line 454: / Line 454: @@
 =GDB ARM=
-To [[DebuggingTheLinuxKernelUsingGdb|debug]] an ARM target with GNU debugger ([[GDB|GDB]]), you need a GDB understanding ARM processor. If your ARM cross compilation tool chain doesn't include a GDB, you can easily build it your self.
+To [[Debugging The Linux Kernel Using Gdb|debug]] an ARM target with GNU debugger ([[GDB]]), you need a GDB understanding ARM processor. If your ARM cross compilation tool chain doesn't include a GDB, you can easily build it your self.
 ==Build==

@@ Line 3: / Line 3: @@
 [[Category:Development Boards]]
 [[Category: BeagleBoard]]
-This page is about how to use open source [http://openocd.berlios.de/web/ OpenOCD] [http://en.wikipedia.org/wiki/JTAG JTAG] software with [[BeagleBoard|BeagleBoard]] and Linux (See [[BeagleBoardOpenOCDWindows|BeagleBoardOpenOCDWindows]] on how to do this with Windows/Cygwin). With this, it will be possible to have OMAP3 JTAG debug using cheap [[BeagleBoardJTAG|JTAG hardware]], e.g. [[BeagleBoardJTAG#TinCanTools_Flyswatter|Flyswatter]].
+This page is about how to use open source [http://openocd.berlios.de/web/ OpenOCD] [http://en.wikipedia.org/wiki/JTAG JTAG] software with [[BeagleBoard|BeagleBoard]] and Linux. With this, it will be possible to have OMAP3 JTAG debug using cheap [[BeagleBoardJTAG|JTAG hardware]], e.g. [[BeagleBoardJTAG#TinCanTools_Flyswatter|Flyswatter]].
 '''As of September 2009, OpenOCD has basic support for OMAP3 and [[BeagleBoardOpenOCD#Cortex_A8_support|ARM Cortex A8]] on Beagle Board. Cortex A8 support is in early alpha stage, a lot is still missing. But e.g. processor halt, resume, step, breakpoints and ARM disassembly of non-Cache and non-MMU (e.g. U-Boot) applications seem to work.

@@ Line 293: / Line 293: @@
 ==Example session==
-Now, we can try to basically halt and resume OMAP3 (assuming U-Boot is running at U-Boot's prompt):
+Now, we can try to basically halt and resume OMAP3 (assuming U-Boot is running at U-Boot's prompt), before doing anything, call omap_dbginit:
-  > '''reset halt'''
+> '''omap3_dbginit omap3530.cpu'''
   RCLK not supported - fallback to 1000 kHz
   JTAG tap: omap3530.jrc tap/device found: 0x0b7ae02f (mfg: 0x017, part: 0xb7ae, ver: 0x0)

@@ Line 295: / Line 295: @@
 Now, we can try to basically halt and resume OMAP3 (assuming U-Boot is running at U-Boot's prompt):
-  > '''omap3_dbginit'''
+  > '''reset halt'''
   JTAG tap: omap3530.jrc tap/device found: 0x0b7ae02f (mfg: 0x017, part: 0xb7ae, ver: 0x0)
-  JTAG Tap/device matched
+  JTAG tap: omap3530.dap enabled
-  AHBAP Cached values: dp_select 0x10, ap_csw 0xa2000002, ap_tar 0x54011080
+  omap3530.cpu: ran after reset and before halt ...
-  SWJ-DP STICKY ERROR
+  target state: halted
-  Read MEM_AP_CSW 0x80000042, MEM_AP_TAR 0x54011080
+  target halted in ARM state due to debug-request, current mode: Supervisor
-    TargetName         Type       Endian TapName            State
+ cpsr: 0x800001d3 pc: 0x40202994
-  --  ------------------ ---------- ------ ------------------ ------------
+  MMU: disabled, D-Cache: disabled, I-Cache: enabled
-* omap3.cpu          cortex_a8  little omap3530.dap       unknown
-x54011314 00000003                            ....
-x54011314 00000001                            ....
   > '''scan_chain'''
-      TapName            | Enabled |   IdCode      Expected    IrLen IrCap  IrMask Instr
+    TapName             Enabled  IdCode     Expected   IrLen IrCap IrMask
-  ---|--------------------|---------|------------|------------|------|------|------|---------
+  -- ------------------- -------- ---------- ---------- ----- ----- ------
-| omap3530.dsp       |    n    | 0x00000000 | 0x00000000 | 0x26 | 0x25 | 0x3f | 0xffffffff
+omap3530.dsp           n     0x00000000 0x00000000    38 0x25  0x3f
-| omap3530.dap       |    Y    | 0x00000000 | 0x0b6d602f | 0x04 | 0x01 | 0x0f | 0x0a
+omap3530.dap           Y     0x00000000 0x0b6d602f     4 0x01  0x0f
-| omap3530.jrc       |    Y    | 0x0b7ae02f | 0x0b7ae02f | 0x06 | 0x01 | 0x3f | 0x3f
+omap3530.jrc           Y     0x0b7ae02f 0x0b7ae02f     6 0x01  0x3f
   > '''halt'''
   target state: halted
@@ Line 327: / Line 332: @@
   spsr_svc: 0x400001d3 pc: 0x80e87dcc
   MMU: disabled, D-Cache: disabled, I-Cache: enabled
   > '''resume'''
@@ Line 350: / Line 398: @@
   MMU: disabled, D-Cache: disabled, I-Cache: enabled
-  > '''armv4_5 disassemble 0x80e88158 10'''
+  > '''arm disassemble 0x80e88158 10'''
 x80e88158      0xe3130001      TST r3, #0x1
 x80e8815c      0x0afffffc      BEQ 0x80e88154