Interrupt Number
|
Signal Name (Non-Ethercat Mode)
|
Source
|
Signal Name (Ethercat Mode)
|
Description
|
63
|
tpcc_int_pend_po1
|
TPCC (EDMA)
|
|
A DMA request has completed
|
62
|
tpcc_errint_pend_po
|
TPCC (EDMA)
|
|
A DMA error has occurred (see TPCC)
|
61
|
tptc_errint_pend_po
|
TPCC (EDMA)
|
|
A DMA error has occurred - TPTC0 only (see TPTC0)
|
60
|
initiator_sinterrupt_q_n1
|
Mbox0 - mail_u1_irq (mailbox interrupt for pru0)
|
|
A message has been left in the mailbox for PRU0 (see Mailbox)
|
59
|
initiator_sinterrupt_q_n2
|
Mbox0 - mail_u2_irq (mailbox interrupt for pru1)
|
|
A message has been left in the mailbox for PRU1 (see Mailbox)
|
58
|
Emulation Suspend Signal (software use)
|
Debugss
|
|
?
|
57
|
POINTRPEND1
|
GPIO0
|
|
Interrupt from level change on an external GPIO0 pin
|
56
|
pwm_trip_zone
|
eHRPWM0/eHRPWM1/eHRPWM2
|
|
External fault occurred on eHRPWM0/1/2 (see Trip-zone)
|
55
|
mcasp_x_intr_pend
|
McASP0 Tx
|
pr1_mii1_crs(external)
|
McASP is ready to receive data for transmitting
|
54
|
mcasp_r_intr_pend
|
McASP0 Rx
|
PRU1_RX_EOF
|
McASP has received an entire frame for processing
|
53
|
gen_intr_pend
|
ADC_TSC
|
MDIO_MII_LINK[1]
|
A general interrupt occurred on the touch controller (check appropriate status register)
|
52
|
nirq
|
UART2
|
PORT1_TX_OVERFLOW
|
A general interrupt occurred on the UART2 (check appropriate status register)
|
51
|
nirq
|
UART0
|
PORT1_TX_UNDERFLOW
|
A general interrupt occurred on the UART0 (check appropriate status register)
|
50
|
c0_rx_thresh_pend
|
3PGSW (GEMAC)
|
PRU1_RX_OVERFLOW
|
External Ethernet switch has passed its receive buffer threshold (ready for data to be retrieved)
|
49
|
c0_rx_pend
|
3PGSW (GEMAC)
|
PRU1_RX_NIBBLE_ODD
|
External Ethernet switch has received a packet (should be acknowledged)
|
48
|
c0_tx_pend
|
3PGSW (GEMAC)
|
PRU1_RX_CRC
|
External Ethernet switch has transmitted a packet (should be acknowledged)
|
47
|
c0_misc_pend
|
3PGSW (GEMAC)
|
PRU1_RX_SOF
|
A miscellaneous interrupt was triggered on the External Ethernet switch (see appropriate status register)
|
46
|
epwm_intr_intr_pend
|
eHRPWM1
|
PRU1_RX_SFD
|
?
|
45
|
eqep_intr_intr_pend
|
eQEP0
|
PRU1_RX_ERR32
|
?
|
44
|
SINTERRUPTN
|
McSPI0
|
PRU1_RX_ERR
|
?
|
43
|
eHRPWM0
|
McASP0 Tx
|
pr1_mii0_crs(external)
|
?
|
42
|
ecap_intr_intr_pend
|
eCAP0
|
PRU0_RX_EOF
|
?
|
41
|
POINTRPEND
|
I2C0
|
MDIO_MII_LINK[0]
|
?
|
40
|
dcan_intr
|
DCAN0
|
PORT0_TX_OVERFLOW
|
?
|
39
|
dcan_int1
|
DCAN0
|
PORT0_TX_UNDERFLOW
|
?
|
38
|
dcan_uerr
|
DCAN0
|
PRU0_RX_OVERFLOW
|
?
|
37
|
epwm_intr_intr_pend
|
eHRPWM2
|
PRU0_RX_NIBBLE_ODD
|
?
|
36
|
ecap_intr_intr_pend
|
eCAP2
|
PRU0_RX_CRC
|
?
|
35
|
ecap_intr_intr_pend
|
eCAP1
|
PRU0_RX_SOF
|
?
|
34
|
mcasp_r_intr_pend
|
McASP1 Rx
|
PRU0_RX_SFD
|
?
|
33
|
mcasp_x_intr_pend
|
McASP1 Tx
|
PRU0_RX_ERR32
|
?
|
32
|
nirq
|
UART1
|
PRU0_RX_ERR
|
?
|
31
|
pr1_pru_mst_intr[15]_intr_req
|
pru0 or pru1
|
|
?
|
30
|
pr1_pru_mst_intr[14]_intr_req
|
pru0 or pru1
|
|
?
|
29
|
pr1_pru_mst_intr[13]_intr_req
|
pru0 or pru1
|
|
?
|
28
|
pr1_pru_mst_intr[12]_intr_req
|
pru0 or pru1
|
|
?
|
27
|
pr1_pru_mst_intr[11]_intr_req
|
pru0 or pru1
|
|
?
|
26
|
pr1_pru_mst_intr[10]_intr_req
|
pru0 or pru1
|
|
?
|
25
|
pr1_pru_mst_intr[9]_intr_req
|
pru0 or pru1
|
|
?
|
24
|
pr1_pru_mst_intr[8]_intr_req
|
pru0 or pru1
|
|
?
|
23
|
pr1_pru_mst_intr[7]_intr_req
|
pru0 or pru1
|
|
?
|
22
|
pr1_pru_mst_intr[6]_intr_req
|
pru0 or pru1
|
|
?
|
21
|
pr1_pru_mst_intr[5]_intr_req
|
pru0 or pru1
|
|
?
|
20
|
pr1_pru_mst_intr[4]_intr_req
|
pru0 or pru1
|
|
?
|
19
|
pr1_pru_mst_intr[3]_intr_req
|
pru0 or pru1
|
|
?
|
18
|
pr1_pru_mst_intr[2]_intr_req
|
pru0 or pru1
|
|
?
|
17
|
pr1_pru_mst_intr[1]_intr_req
|
pru0 or pru1
|
|
?
|
16
|
pr1_pru_mst_intr[0]_intr_req
|
pru0 or pru1
|
PRUSS Internal Interrupts
|
?
|
15
|
pr1_ecap_intr_req
|
PRUSS eCAP
|
|
?
|
14
|
sync0_out_pend
|
PRUSS IEP (Ethercat)
|
|
?
|
13
|
sync1_out_pend
|
PRUSS IEP (Ethercat)
|
|
?
|
12
|
latch0_in(input to PRUSS)
|
PRUSS IEP (Ethercat)
|
|
?
|
11
|
latch1_in(input to PRUSS)
|
PRUSS IEP (Ethercat)
|
|
?
|
10
|
pdi_wd_exp_pend
|
PRUSS IEP (Ethercat)
|
|
?
|
9
|
pd_wd_exp_pend
|
PRUSS IEP (Ethercat)
|
|
?
|
8
|
digio_event_req
|
PRUSS IEP (Ethercat)
|
|
?
|
7
|
pr1_iep_tim_cap_cmp_pend
|
PRUSS IEP (Ethercat)
|
|
?
|
6
|
pr1_uart_uint_intr_req
|
PRUSS UART
|
|
?
|
5
|
pr1_uart_utxevt_intr_req
|
PRUSS UART
|
|
?
|
4
|
pr1_uart_urxevt_intr_req
|
PRUSS UART
|
|
?
|
3
|
pr1_xfr_timeout
|
PRUSS Scratch Pad
|
|
Simultaneous Scratch Pad access from both PRUs caused access time-out after 1024 cycles
|
2
|
pr1_pru1_r31_status_cnt16
|
PRU1 (Shift Capture)
|
|
?
|
1
|
pr1_pru0_r31_status_cnt16
|
PRU0 (Shift Capture)
|
|
?
|
0
|
pr1_parity_err_intr_pend
|
PRUSS Parity Logic
|
|
?
|