diff -urN ./ppcboot-1.1.6.orig/Makefile ./ppcboot-1.1.6/Makefile --- ./ppcboot-1.1.6.orig/Makefile 2002-06-10 10:09:10.000000000 -0600 +++ ./ppcboot-1.1.6/Makefile 2006-01-31 19:43:37.000000000 -0700 @@ -36,7 +36,7 @@ ifeq ($(HOSTARCH),ppc) CROSS_COMPILE = else -CROSS_COMPILE = powerpc-$(HOSTOS)- +CROSS_COMPILE = /usr5/A3000/buildroot/build_powerpc/staging_dir/bin/powerpc-$(HOSTOS)- endif endif diff -urN ./ppcboot-1.1.6.orig/board/walnut405/config.mk ./ppcboot-1.1.6/board/walnut405/config.mk --- ./ppcboot-1.1.6.orig/board/walnut405/config.mk 2001-01-22 11:17:14.000000000 -0700 +++ ./ppcboot-1.1.6/board/walnut405/config.mk 2006-02-03 21:50:14.000000000 -0700 @@ -26,4 +26,4 @@ # #TEXT_BASE = 0xFFFE0000 -TEXT_BASE = 0xFFF80000 +TEXT_BASE = 0xfff80000 diff -urN ./ppcboot-1.1.6.orig/board/walnut405/flash.c ./ppcboot-1.1.6/board/walnut405/flash.c --- ./ppcboot-1.1.6.orig/board/walnut405/flash.c 2002-01-12 17:10:36.000000000 -0700 +++ ./ppcboot-1.1.6/board/walnut405/flash.c 2006-02-03 20:37:19.000000000 -0700 @@ -344,7 +344,7 @@ #endif switch (value) { - case (FLASH_WORD_SIZE)AMD_ID_F040B: + case (FLASH_WORD_SIZE)AMD_ID_LV040B: info->flash_id += FLASH_AM040; info->sector_count = 8; info->size = 0x0080000; /* => 512 ko */ diff -urN ./ppcboot-1.1.6.orig/board/walnut405/ppcboot.lds ./ppcboot-1.1.6/board/walnut405/ppcboot.lds --- ./ppcboot-1.1.6.orig/board/walnut405/ppcboot.lds 2001-04-28 11:59:12.000000000 -0600 +++ ./ppcboot-1.1.6/board/walnut405/ppcboot.lds 2006-01-31 19:27:17.000000000 -0700 @@ -27,11 +27,12 @@ __DYNAMIC = 0; */ SECTIONS { +/* .resetvec 0xFFFFFFFC : { *(.resetvec) } = 0xffff - +*/ /* Read-only sections, merged into text segment: */ . = + SIZEOF_HEADERS; .interp : { *(.interp) } diff -urN ./ppcboot-1.1.6.orig/board/walnut405/walnut405.c ./ppcboot-1.1.6/board/walnut405/walnut405.c --- ./ppcboot-1.1.6.orig/board/walnut405/walnut405.c 2002-03-10 07:37:15.000000000 -0700 +++ ./ppcboot-1.1.6/board/walnut405/walnut405.c 2006-02-03 21:45:16.000000000 -0700 @@ -91,25 +91,13 @@ int checkboard (void) { - unsigned char *s = getenv("serial#"); - unsigned char *e; - - if (!s || strncmp(s, "WALNUT405", 9)) - { - printf ("### No HW ID - assuming WALNUT405"); - } - else - { - for (e=s; *e; ++e) { - if (*e == ' ') - break; - } - - for ( ; s #include -#include +#if !defined(CONFIG_440) #include <405gp_pci.h> +#endif #include #include -#ifdef CONFIG_405GP +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) #ifdef CONFIG_PCI /*#define DEBUG*/ /*-----------------------------------------------------------------------------+ -| pci_init. Initializes the 405GP PCI Configuration regs. -+-----------------------------------------------------------------------------*/ + * pci_init. Initializes the 405GP PCI Configuration regs. + *-----------------------------------------------------------------------------*/ void pci_405gp_init(bd_t *bd, struct pci_controller *hose) { - int i, reg_num = 0; - unsigned short temp_short; - unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; -#if defined(CONFIG_CPCI405) - unsigned long ptmla[2] = {bd->bi_memstart, bd->bi_flashstart}; - unsigned long ptmms[2] = {~(bd->bi_memsize - 1) | 1, ~(bd->bi_flashsize - 1) | 1}; -#else - unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; - unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; -#endif -#if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) - unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; - unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; - unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; - unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; -#else - unsigned long pmmla[3] = {0x80000000, 0,0}; - unsigned long pmmma[3] = {0xC0000001, 0,0}; - unsigned long pmmpcila[3] = {0x80000000, 0,0}; - unsigned long pmmpciha[3] = {0x00000000, 0,0}; -#endif + int i, reg_num = 0; + + unsigned short temp_short; + unsigned long ptmpcila[2] = {CFG_PCI_PTM1PCI, CFG_PCI_PTM2PCI}; + unsigned long ptmla[2] = {CFG_PCI_PTM1LA, CFG_PCI_PTM2LA}; + unsigned long ptmms[2] = {CFG_PCI_PTM1MS, CFG_PCI_PTM2MS}; + unsigned long pmmla[3] = {0x80000000, 0,0}; + unsigned long pmmma[3] = {0xC0000001, 0,0}; + unsigned long pmmpcila[3] = {0x80000000, 0,0}; + unsigned long pmmpciha[3] = {0x00000000, 0,0}; - /* - * Register the hose - */ - hose->first_busno = 0; - hose->last_busno = 0xff; - - /* ISA/PCI I/O space */ - pci_set_region(hose->regions + reg_num++, - MIN_PCI_PCI_IOADDR, - MIN_PLB_PCI_IOADDR, - 0x10000, - PCI_REGION_IO); - - /* PCI I/O space */ - pci_set_region(hose->regions + reg_num++, - 0x00800000, - 0xe8800000, - 0x03800000, - PCI_REGION_IO); - - reg_num = 2; - - /* Memory spaces */ - for (i=0; i<2; i++) - if (ptmms[i] & 1) - { - if (!i) hose->pci_fb = hose->regions + reg_num; - - pci_set_region(hose->regions + reg_num++, - ptmpcila[i], ptmla[i], - ~(ptmms[i] & 0xfffff000) + 1, - PCI_REGION_MEM | - PCI_REGION_MEMORY); - } - - /* PCI memory spaces */ - for (i=0; i<3; i++) - if (pmmma[i] & 1) - { - pci_set_region(hose->regions + reg_num++, - pmmpcila[i], pmmla[i], - ~(pmmma[i] & 0xfffff000) + 1, - PCI_REGION_MEM); - } - - hose->region_count = reg_num; - - pci_setup_indirect(hose, - PCICFGADR, - PCICFGDATA); - - if (hose->pci_fb) - pciauto_region_init(hose->pci_fb); - - pci_register_hose(hose); - - /*--------------------------------------------------------------------------+ - | 405GP PCI Master configuration. - | Map one 512 MB range of PLB/processor addresses to PCI memory space. - | PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF - | Use byte reversed out routines to handle endianess. - +--------------------------------------------------------------------------*/ - out32r(PMM0MA, pmmma[0]); /* ensure disabled b4 setting PMM0LA */ - out32r(PMM0LA, pmmla[0]); - out32r(PMM0PCILA, pmmpcila[0]); - out32r(PMM0PCIHA, pmmpciha[0]); - out32r(PMM0MA, pmmma[0]); - - /*--------------------------------------------------------------------------+ - | PMM1 is not used. Initialize them to zero. - +--------------------------------------------------------------------------*/ - out32r(PMM1MA, pmmma[1]); /* ensure disabled b4 setting PMM2LA */ - out32r(PMM1LA, pmmla[1]); - out32r(PMM1PCILA, pmmpcila[1]); - out32r(PMM1PCIHA, pmmpciha[1]); - out32r(PMM1MA, pmmma[1]); - - /*--------------------------------------------------------------------------+ - | PMM2 is not used. Initialize them to zero. - +--------------------------------------------------------------------------*/ - out32r(PMM2MA, pmmma[2]); /* ensure disabled b4 setting PMM2LA */ - out32r(PMM2LA, pmmla[2]); - out32r(PMM2PCILA, pmmpcila[2]); - out32r(PMM2PCIHA, pmmpciha[2]); - out32r(PMM2MA, pmmma[2]); - - /*--------------------------------------------------------------------------+ - | 405GP PCI Target configuration. (PTM1) - | Note: PTM1MS is hardwire enabled but we set the enable bit anyway. - +--------------------------------------------------------------------------*/ - out32r(PTM1LA, ptmla[0]); /* insert address */ - out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ - - /*--------------------------------------------------------------------------+ - | 405GP PCI Target configuration. (PTM2) - +--------------------------------------------------------------------------*/ - out32r(PTM2LA, ptmla[1]); /* insert address */ - if (ptmms[1] == 0) - { - out32r(PTM2MS, 0x00000001); /* set enable bit */ - pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); - out32r(PTM2MS, 0x00000000); /* disable */ - } - else - { - out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ - } - - /* - * Insert Subsystem Vendor and Device ID - */ - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); -#ifdef CONFIG_CPCI405 - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); - else - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID2); -#else - pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); +#ifdef CONFIG_PCI_PNP +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + char *s; +#endif #endif - /* - * Insert Class-code - */ + /* + * Register the hose + */ + hose->first_busno = 0; + hose->last_busno = 0xff; + + /* ISA/PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + MIN_PCI_PCI_IOADDR, + MIN_PLB_PCI_IOADDR, + 0x10000, + PCI_REGION_IO); + + /* PCI I/O space */ + pci_set_region(hose->regions + reg_num++, + 0x00800000, + 0xe8800000, + 0x03800000, + PCI_REGION_IO); + + reg_num = 2; + + /* Memory spaces */ + for (i=0; i<2; i++) + if (ptmms[i] & 1) + { + if (!i) hose->pci_fb = hose->regions + reg_num; + + pci_set_region(hose->regions + reg_num++, + ptmpcila[i], ptmla[i], + ~(ptmms[i] & 0xfffff000) + 1, + PCI_REGION_MEM | + PCI_REGION_MEMORY); + } + + /* PCI memory spaces */ + for (i=0; i<3; i++) + if (pmmma[i] & 1) + { + pci_set_region(hose->regions + reg_num++, + pmmpcila[i], pmmla[i], + ~(pmmma[i] & 0xfffff000) + 1, + PCI_REGION_MEM); + } + + hose->region_count = reg_num; + + pci_setup_indirect(hose, + PCICFGADR, + PCICFGDATA); + + if (hose->pci_fb) + pciauto_region_init(hose->pci_fb); + + pci_register_hose(hose); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Master configuration. + * Map one 512 MB range of PLB/processor addresses to PCI memory space. + * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF + * Use byte reversed out routines to handle endianess. + *--------------------------------------------------------------------------*/ + + out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */ + out32r(PMM0LA, pmmla[0]); + out32r(PMM0PCILA, pmmpcila[0]); + out32r(PMM0PCIHA, pmmpciha[0]); + out32r(PMM0MA, pmmma[0]); + + /*--------------------------------------------------------------------------+ + * PMM1 is not used. Initialize them to zero. + *--------------------------------------------------------------------------*/ + out32r(PMM1MA, (pmmma[1]&~0x1)); + out32r(PMM1LA, pmmla[1]); + out32r(PMM1PCILA, pmmpcila[1]); + out32r(PMM1PCIHA, pmmpciha[1]); + out32r(PMM1MA, pmmma[1]); + + /*--------------------------------------------------------------------------+ + * PMM2 is not used. Initialize them to zero. + *--------------------------------------------------------------------------*/ + out32r(PMM2MA, (pmmma[2]&~0x1)); + out32r(PMM2LA, pmmla[2]); + out32r(PMM2PCILA, pmmpcila[2]); + out32r(PMM2PCIHA, pmmpciha[2]); + out32r(PMM2MA, pmmma[2]); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Target configuration. (PTM1) + * Note: PTM1MS is hardwire enabled but we set the enable bit anyway. + *--------------------------------------------------------------------------*/ + out32r(PTM1LA, ptmla[0]); /* insert address */ + out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]); + + /*--------------------------------------------------------------------------+ + * 405GP PCI Target configuration. (PTM2) + *--------------------------------------------------------------------------*/ + out32r(PTM2LA, ptmla[1]); /* insert address */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]); + + if (ptmms[1] == 0) + { + out32r(PTM2MS, 0x00000001); /* set enable bit */ + pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); + out32r(PTM2MS, 0x00000000); /* disable */ + } + else + { + out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ + } + + /* + * Insert Subsystem Vendor and Device ID + */ + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CFG_PCI_SUBSYS_VENDORID); + pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_DEVICEID); + + /* + * Insert Class-code + */ #ifdef CFG_PCI_CLASSCODE - pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE); + pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CFG_PCI_CLASSCODE); #endif /* CFG_PCI_CLASSCODE */ - /*--------------------------------------------------------------------------+ - | If PCI speed = 66Mhz, set 66Mhz capable bit. - +--------------------------------------------------------------------------*/ - if (bd->bi_pci_busfreq >= 66000000) { - pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); - pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); - } + /*--------------------------------------------------------------------------+ + * If PCI speed = 66Mhz, set 66Mhz capable bit. + *--------------------------------------------------------------------------*/ + if (bd->bi_pci_busfreq >= 66000000) { + pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); + pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); + } #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) -#if (CONFIG_PCI_HOSE == PCI_HOST_AUTO) - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) +#if (CONFIG_PCI_HOST == PCI_HOST_AUTO) + if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) #endif - { - /*--------------------------------------------------------------------------+ - | Write the 405GP PCI Configuration regs. - | Enable 405GP to be a master on the PCI bus (PMM). - | Enable 405GP to act as a PCI memory target (PTM). - +--------------------------------------------------------------------------*/ - pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); - pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | - PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - } + { + /*--------------------------------------------------------------------------+ + * Write the 405GP PCI Configuration regs. + * Enable 405GP to be a master on the PCI bus (PMM). + * Enable 405GP to act as a PCI memory target (PTM). + *--------------------------------------------------------------------------*/ + pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + } #endif - /* - * Set HCE bit (Host Configuration Enabled) - */ - pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); - pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); + + /* + * Set HCE bit (Host Configuration Enabled) + */ + pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); + pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); #ifdef CONFIG_PCI_PNP - /*--------------------------------------------------------------------------+ - | Scan the PCI bus and configure devices found. - +--------------------------------------------------------------------------*/ + /*--------------------------------------------------------------------------+ + * Scan the PCI bus and configure devices found. + *--------------------------------------------------------------------------*/ #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) - if (mfdcr(strap) & PSR_PCI_ARBIT_EN) + if ((mfdcr(strap) & PSR_PCI_ARBIT_EN) || + (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) #endif - { + { #ifdef CONFIG_PCI_SCAN_SHOW - printf("PCI: Bus Dev VenId DevId Class Int\n"); + printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif - hose->last_busno = pci_hose_scan(hose); - } + hose->last_busno = pci_hose_scan(hose); + } #endif /* CONFIG_PCI_PNP */ } @@ -293,11 +289,11 @@ * the auto setup of a PCI device disabling what is done pci_405gp_init * as has happened before. */ -void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev, - struct pci_config_table *entry) +void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *entry) { -#ifdef DEBUG - printf("405gp_setup_bridge\n"); +#ifdef DEBUG + printf("405gp_setup_bridge\n"); #endif } @@ -307,41 +303,41 @@ void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) { - unsigned char int_line = 0xff; + unsigned char int_line = 0xff; - /* - * Write pci interrupt line register (cpci405 specific) - */ - switch (PCI_DEV(dev) & 0x03) - { - case 0: - int_line = 27 + 2; - break; - case 1: - int_line = 27 + 3; - break; - case 2: - int_line = 27 + 0; - break; - case 3: - int_line = 27 + 1; - break; - } + /* + * Write pci interrupt line register (cpci405 specific) + */ + switch (PCI_DEV(dev) & 0x03) + { + case 0: + int_line = 27 + 2; + break; + case 1: + int_line = 27 + 3; + break; + case 2: + int_line = 27 + 0; + break; + case 3: + int_line = 27 + 1; + break; + } - pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); + pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); } -void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, +void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, struct pci_config_table *entry) { - unsigned int cmdstat = 0; + unsigned int cmdstat = 0; - pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); + pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); - /* always enable io space on vga boards */ - pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); - cmdstat |= PCI_COMMAND_IO; - pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); + /* always enable io space on vga boards */ + pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); + cmdstat |= PCI_COMMAND_IO; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); } #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) @@ -349,33 +345,33 @@ /* *As is these functs get called out of flash Not a horrible *thing, but something to keep in mind. (no statics?) -*/ + */ static struct pci_config_table pci_405gp_config_table[] = { /*if VendID is 0 it terminates the table search (ie Walnut)*/ -#if CFG_PCI_SUBSYS_VENDORID - {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, +#ifdef CFG_PCI_SUBSYS_VENDORID + {CFG_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, #endif - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, - {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, - PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, + {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, - { } + { } }; static struct pci_controller hose = { - fixup_irq: pci_405gp_fixup_irq, - config_table: pci_405gp_config_table, + fixup_irq: pci_405gp_fixup_irq, + config_table: pci_405gp_config_table, }; void pci_init(bd_t *bd) { - /*we want the ptrs to RAM not flash (ie don't use init list)*/ - hose.fixup_irq = pci_405gp_fixup_irq; - hose.config_table = pci_405gp_config_table; - pci_405gp_init(bd, &hose); + /*we want the ptrs to RAM not flash (ie don't use init list)*/ + hose.fixup_irq = pci_405gp_fixup_irq; + hose.config_table = pci_405gp_config_table; + pci_405gp_init(bd, &hose); } #endif diff -urN ./ppcboot-1.1.6.orig/cpu/ppc4xx/config.mk ./ppcboot-1.1.6/cpu/ppc4xx/config.mk --- ./ppcboot-1.1.6.orig/cpu/ppc4xx/config.mk 2001-09-10 17:03:25.000000000 -0600 +++ ./ppcboot-1.1.6/cpu/ppc4xx/config.mk 2006-01-31 19:29:52.000000000 -0700 @@ -21,6 +21,6 @@ # MA 02111-1307 USA # -PLATFORM_RELFLAGS += -mrelocatable -ffixed-r14 -meabi +PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -mcpu=403 -msoft-float diff -urN ./ppcboot-1.1.6.orig/cpu/ppc4xx/spd_sdram.c ./ppcboot-1.1.6/cpu/ppc4xx/spd_sdram.c --- ./ppcboot-1.1.6.orig/cpu/ppc4xx/spd_sdram.c 2002-03-15 05:36:08.000000000 -0700 +++ ./ppcboot-1.1.6/cpu/ppc4xx/spd_sdram.c 2006-02-04 17:43:43.000000000 -0700 @@ -129,6 +129,7 @@ int t_rcd; int t_rc = 70; /* This value not available in SPD_EEPROM */ int min_cas = 2; + int i; /* * Make sure I2C controller is initialized @@ -403,7 +404,7 @@ #define mtsdram0(reg, data) mtdcr(memcfga,reg);mtdcr(memcfgd,data) - /* disable memcontroller so updates work */ + /* disable memcontroller so updates work. for ram based config comment out next 2 lines */ sdram0_cfg = 0; mtsdram0( mem_mcopt1, sdram0_cfg ); diff -urN ./ppcboot-1.1.6.orig/cpu/ppc4xx/start.S ./ppcboot-1.1.6/cpu/ppc4xx/start.S --- ./ppcboot-1.1.6.orig/cpu/ppc4xx/start.S 2002-06-07 09:17:11.000000000 -0600 +++ ./ppcboot-1.1.6/cpu/ppc4xx/start.S 2006-02-02 20:36:46.000000000 -0700 @@ -133,7 +133,7 @@ GOT_ENTRY(transfer_to_handler) GOT_ENTRY(_end) - GOT_ENTRY(.bss) + GOT_ENTRY(__bss_start) END_GOT /* @@ -1044,6 +1044,7 @@ addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET mtlr r0 +// b 0 /* spin here for debug */ blr /* NEVER RETURNS! */ in_ram: @@ -1086,7 +1087,7 @@ /* * Now clear BSS segment */ - lwz r3,GOT(.bss) + lwz r3,GOT(__bss_start) lwz r4,GOT(_end) cmplw 0, r3, r4 diff -urN ./ppcboot-1.1.6.orig/disk/part.c ./ppcboot-1.1.6/disk/part.c --- ./ppcboot-1.1.6.orig/disk/part.c 2002-01-18 04:04:59.000000000 -0700 +++ ./ppcboot-1.1.6/disk/part.c 2006-02-03 15:09:54.000000000 -0700 @@ -26,7 +26,7 @@ #include #include -#undef PART_DEBUG +#define PART_DEBUG #ifdef PART_DEBUG #define PRINTF(fmt,args...) printf (fmt ,##args) diff -urN ./ppcboot-1.1.6.orig/drivers/pci_auto.c ./ppcboot-1.1.6/drivers/pci_auto.c --- ./ppcboot-1.1.6.orig/drivers/pci_auto.c 2002-04-02 06:22:45.000000000 -0700 +++ ./ppcboot-1.1.6/drivers/pci_auto.c 2006-02-05 21:38:41.000000000 -0700 @@ -83,13 +83,14 @@ { unsigned int bar_value, bar_response, bar_size; unsigned int cmdstat = 0; + unsigned short class; struct pci_region *bar_res; int bar, bar_nr = 0; int found_mem64 = 0; pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER; - + for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) { /* Tickle the BAR and get the response */ @@ -103,6 +104,9 @@ found_mem64 = 0; /* Check the BAR type and set our address mask */ + + DBG("bar_response: 0x%x,BAR =0x%x, ", bar_response, bar); + if (bar_response & PCI_BASE_ADDRESS_SPACE) { bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1; @@ -147,6 +151,10 @@ bar_nr++; } + pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class); + + if (class == PCI_CLASS_BRIDGE_HOST) cmdstat |= 0x06; + pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08); pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80); @@ -301,11 +309,11 @@ case PCI_CLASS_STORAGE_IDE: pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface); - if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) - { - DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n"); - return; - } +// if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) +// { +// DBG("PCI Autoconfig: Skipping legacy mode IDE controller\n"); +// return; +// } pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_io); break; diff -urN ./ppcboot-1.1.6.orig/include/config_WALNUT405.h ./ppcboot-1.1.6/include/config_WALNUT405.h --- ./ppcboot-1.1.6.orig/include/config_WALNUT405.h 2002-03-31 11:30:38.000000000 -0700 +++ ./ppcboot-1.1.6/include/config_WALNUT405.h 2006-02-03 21:49:59.000000000 -0700 @@ -39,8 +39,8 @@ #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ -/*#define CFG_ENV_IS_IN_FLASH 1*/ /* use FLASH for environment vars */ -#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ +#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +/*#define CFG_ENV_IS_IN_NVRAM 1 */ /* use NVRAM for environment vars */ #ifdef CFG_ENV_IS_IN_NVRAM #undef CFG_ENV_IS_IN_FLASH @@ -54,7 +54,7 @@ #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ #if 1 -#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */ +#define CONFIG_BOOTCOMMAND "diskboot 100000 0 ; bootm" /* autoboot command */ #else #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */ #endif @@ -74,8 +74,8 @@ "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4" #else -#define CONFIG_BOOTARGS "root=/dev/hda1 " \ - "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" +#define CONFIG_BOOTARGS "root=/dev/hda1 " +// "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0" #endif @@ -83,16 +83,16 @@ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_PHY_ADDR 9 /* PHY address */ #define CONFIG_RTC_DS174x 1 /* use DS1743 RTC in Walnut */ #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ CFG_CMD_PCI | \ CFG_CMD_IRQ | \ - CFG_CMD_KGDB | \ CFG_CMD_DHCP | \ CFG_CMD_DATE | \ + CFG_CMD_IDE | \ CFG_CMD_BEDBUG | \ CFG_CMD_ELF ) @@ -181,13 +181,31 @@ #define CFG_IR_REG_BASE_ADDR 0xF0200000 #define CFG_FPGA_REG_BASE_ADDR 0xF0300000 +/************************************************************ + * IDE/ATA stuff + ************************************************************/ +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */ +#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ + +#define CFG_ATA_BASE_ADDR 0xe8000000 /* base address */ +#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ +/* #define CFG_ATA_IDE1_OFFSET 0x0170 */ /* ide1 offset */ +#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CFG_ATA_REG_OFFSET 0 /* reg offset */ +#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ + +#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */ +#undef CONFIG_IDE_LED /* no led for ide supported */ +#undef CONFIG_IDE_RESET /* reset for ide supported... */ +#undef CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ + /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CFG_SDRAM_BASE _must_ start at 0 */ #define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 +#define CFG_FLASH_BASE 0xfff80000 #define CFG_MONITOR_BASE CFG_FLASH_BASE #define CFG_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ @@ -209,6 +227,7 @@ /* BEG ENVIRONNEMENT FLASH */ #ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_ADDR 0xfffb0000 /* put env at fixed address for test */ #define CFG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */ #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */ @@ -240,7 +259,7 @@ * BR0/1 and OR0/1 (FLASH) */ -#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */ +#define FLASH_BASE0_PRELIM 0xFFF80000 /* FLASH bank #0 */ #define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ @@ -262,7 +281,13 @@ * Definitions for Serial Presence Detect EEPROM address * (to get SDRAM settings) */ -#define SPD_EEPROM_ADDRESS 0x50 +#define SPD_EEPROM_ADDRESS 0xA0 +/************************************************************ + * DISK Partition support + ************************************************************/ +#define CONFIG_DOS_PARTITION +#define CONFIG_MAC_PARTITION +#define CONFIG_ISO_PARTITION /* Experimental */ /* * Internal Definitions diff -urN ./ppcboot-1.1.6.orig/include/linux/mtd/nftl.h ./ppcboot-1.1.6/include/linux/mtd/nftl.h --- ./ppcboot-1.1.6.orig/include/linux/mtd/nftl.h 2002-01-25 17:07:42.000000000 -0700 +++ ./ppcboot-1.1.6/include/linux/mtd/nftl.h 2006-01-31 19:56:52.000000000 -0700 @@ -90,7 +90,7 @@ __u16 lastEUN; /* should be suppressed */ __u16 numfreeEUNs; __u16 LastFreeEUN; /* To speed up finding a free EUN */ - __u32 long nr_sects; + __u32 nr_sects; int head,sect,cyl; __u16 *EUNtable; /* [numvunits]: First EUN for each virtual unit */ __u16 *ReplUnitTable; /* [numEUNs]: ReplUnitNumber for each */ diff -urN ./ppcboot-1.1.6.orig/maker.sh ./ppcboot-1.1.6/maker.sh --- ./ppcboot-1.1.6.orig/maker.sh 1969-12-31 17:00:00.000000000 -0700 +++ ./ppcboot-1.1.6/maker.sh 2006-02-02 19:53:33.000000000 -0700 @@ -0,0 +1,5 @@ +#!/bin/sh + +make distclean +make WALNUT405_config +make diff -urN ./ppcboot-1.1.6.orig/tools/gdb/astest.c ./ppcboot-1.1.6/tools/gdb/astest.c --- ./ppcboot-1.1.6.orig/tools/gdb/astest.c 2001-10-23 05:55:05.000000000 -0600 +++ ./ppcboot-1.1.6/tools/gdb/astest.c 2006-01-31 19:44:06.000000000 -0700 @@ -81,7 +81,7 @@ close(ifd); Error("bfd_fdopenr of file '%s' failed", ifn); } - bfdp->cacheable = true; + bfdp->cacheable = 1; if (!bfd_check_format(bfdp, bfd_object) || (bfd_get_file_flags(bfdp) & EXEC_P) == 0) {