Jetson TX2/FAQ

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Here we share some useful FAQs for Jetson TX2.

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Design with module

Why TX2 uses AO-therm instead of GPU-therm (used on TX1) to monitor GPU thermal?

tags: AO-therm, GPU-therm

The real reason is GPU TSOSC cannot run below certain VDD_GPU voltages. We have a fallback mechanism for this, but for many reasons we decided the better solution is to just use AOTAG always. The AOTAG’s proximity to GPU complex is one of the reasons why this is able to be the best option.

What's the Ethernet chip in TX2?

tags: Ethernet

The Ethernet part U505 in schematic and BOM is marked as BCM89610A2BMLG, but also marked in same page of schematic as BCM546(2)10C1IMLG. BCM54610, BCM54620, and BCM89610 are all pin compatible device, at one time, BCM54620 was chosen because it can support WOL, but its temperature range can’t meet module requirement. So, auto grade part 89610 was in the BOM.

How to cluster TX1&TX2?

tags: Cluster

In theory if user has a carrier board with nontransparent-capable PCIe switch between two Jetson nodes, that could do it.

The recommended padstack for SEAM connector

tags: Samtec, Solder Charge Technology

General pad has smaller stencil/solder masker opening, but for SEAM connector, Samtec suggest larger opening because of their Solder Charge Technology. On Jetson the pad size is 0.64mm, stencil opening is 0.89mm and solder masker opening is 0.74mm.

Ethernet LOM-LED mode

tags: ethernet, LOM-LED

If the pull-up on DMIC4_CLK means the ethernet chip will enter LOM-LED mode? Yes it will enter LOM-LED mode with that pull-up but only if the shadow value of register 1CH is 01011, so the default pin function of LED4 (DMIC4_CLK) is not to set LOM-LED mode.

Why the value of thermal zone 6 is always 100000?

tags: thermal zone 6

The value of thermal zone 6 is always 100000. The reason is the PMIC doesn't allow software to read an actual temperature. Software can only read whether various thermal thresholds have been crossed. The first threshold is higher than 100C. So, the PMIC driver *assumes* temperature is 100C until it learns that it is even higher.

Jetson TX2 FAQ

USB/PCIE/SATA mapping difference between Jetson_TX1 and Jetson_TX2

tags: USB3, PCIe, SATA, mapping

Question :

How many PCIe controllers on TX2 chip and what's the difference comparing with TX1?


TX2 CVM support 3 PCIe controllers( PCIe#0, PCIe#1, and PCIe#2). And on our carrier board(CB), we use Config 2 as default which only use 1 controller: PCIe#0 x4.

USB_SS0 and PEX1 share same Tegra lane (lane0) on CVM (by a MUX controlled by QSPI_IO2(GPIO_R03)), and default configuration is USB_SS0.

Tx2 mapping.png

TX1 support 2 PCIe controllers (PCIe#0 and PCIe#1). On our carrier board, we use config 1 as default: PCIe#0 x4, and PCIe#1 x1.

Tx1 mapping.png


Is Lane 2 and Lane 3 on TX2 reversed comparing with the TX1 module?


On above table 15 of TX2 and Table 14 of TX1, showing “Lane 2 and Lane 3 reversed”. Users don’t need to care about this. It’s CVM internal connection reversed.

For out of CVM , the mapping are same for both TX1 and TX2:




How to design carrier board which TX1 and TX2 pin compatible for USB/SATA/PCIe?


For backward and forward compatible between TX1 and TX2, you can use below configurations:

Tx1 Tx2compatible.png

How to change power mode?

Tags: nvpmodel, power mode

We can change the default Power mode or modify the online_Cores&Freq in /etc/nvpmodel.conf. Or change power mode by "#nvpmodel -m x" ( x - Mode ID ) in runtime.


What's the PAD drive strength of TX2?

Tags: PAD, drive strength

The data of drive strength is contained in JetsonTX2_OEM_Product_Design_Guide.pdf.


What's the mapping between Thermal Zones and sysfs node?

Tags: thermal_zones

The Tegra junction temperature can be directly read from sysfs nodes, as shown in the following example. Note that the name of each temperature zone is noted in the type node and that the temperature values are reported in units of m °C.

  1. cat /sys/devices/virtual/thermal/thermal_zone4/type


  1. cat /sys/devices/virtual/thermal/thermal_zone4/temp


Thermal zones.png

What's the usage of UART7?

Tags: uart7, BPMP

The UART7 port (pin D5, D8) is RSVD on TX1 and used as uart port on TX2, but it is only used for BMPM debugging and so can not be used for other purpose.

How to understand "GPIO controllers with each three interrupts"?

Tags: GPIO, Interrupt

In page 69 of TRM, it says "Six GPIO controllers with each three interrupts", and on current dev kit pinmux, all possible GPIOs are marked as, and pin Power_BTN FORCE_RECOV_BTN ,VOL_DOWN are set as interrupts, so if it illustrates that no possible to set other GPIO_3 pin as interrupt? There are 6 GPIO controllers in the Non-AON domain in T186, each of the controller is having 3 interrupts assigned to it. All the pins in each GPIO controller are interrupt capable. The document is talking about hard interrupt. Once the interrupt received, controller gets to know the gpio number by reading status register.

What is the Link Control 2 and Link Status 2 Registers Address?

Tags: PCIE, address

Regarding the address of register T_PCIE2_RP_LINK_CONTROL_STATUS_2, our TRM is not much clear about how to choose the base address of it. Use tegrashell to list the address are as below:


10001090: PCIE2_RP_LINK_CONTROL_STATUS_1 = 0x00000000 //

100010b0: PCIE2_RP_LINK_CONTROL_STATUS_2_1 = 0x00000000 //

10004090: PCIE2_RP_LINK_CONTROL_STATUS_2 = 0x00000000 //

100040b0: PCIE2_RP_LINK_CONTROL_STATUS_2_2 = 0x00000000 //

10000090: PCIE2_RP_LINK_CONTROL_STATUS_0 = 0x00000000 //

100000b0: PCIE2_RP_LINK_CONTROL_STATUS_2_0 = 0x00000000 //

Note: The "T-" means Tegra, it is same w/ or w/o it in the register name. Per Chun-Hung Lai's comment: This is an artifact of the reference manuals these register specs originated from, where project prefixes are adding before all register names.

Two kinds of OTG cable

Tags: OTG cable

In topic 1030635 , users met the problem that the USB3.0 port only support device mode while not OTG mode, there are two kinds of OTG cable in market, only one has twisted TX/RX lines.