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==About your project== | ==About your project== | ||
| − | ''Project name'': | + | ''Project name'': Beaglewire Software Support<br> |
===Description=== | ===Description=== | ||
In 10-20 sentences, what are you making, for whom, why and with what technologies (programming languages, etc.)? (We are looking for open source SOFTWARE submissions.) | In 10-20 sentences, what are you making, for whom, why and with what technologies (programming languages, etc.)? (We are looking for open source SOFTWARE submissions.) | ||
| + | ;Introduction | ||
| + | Beagle Wire is an FPGA Cape for the beaglebone black. In this project, I'm developing and testing the existing software support of Beaglewire. The known primary issue in Beaglewire is the interface between 32MB SDRAM and ICE40HX4K. For this Solution, I'm going to try LiteDRAM(a small footprint and configurable DRAM core). There are two grove Connectors on BeagleWire for I2C, I'm going to found whether there is improvement needed in the existing I2C Verilog code and will also provide some example code with simple I2C sensors. <br> | ||
| + | I will also test Subsystems like PWM, UART in actual hardware, if found not working will correct the subsystems and provide appropriate examples codes for them. | ||
===Timeline=== | ===Timeline=== | ||
Revision as of 10:48, 5 April 2021
Contents
Proposal for Beaglewire Updates
About
Student: Omkar Bhilare
Mentors: Michael Welling
Code: gsoc-application
Wiki: https://elinux.org/BeagleBoard/GSoC/2021_Proposal/OmkarBhilare
GSoC: GSoC entry
Status
This project is currently just a proposal.
Proposal
Completed All the requirements listed on the ideas page.
The PR request for cross-compilation task: #154.
About you
IRC: Omkar Bhilare
Github: ombhilare999
School: Veermata Jijabai Technological Institute
Country: India
Primary language : English, Hindi, Marathi
Typical work hours: 10AM-8PM Indian Standard Time
Previous GSoC participation: This is my first time applying for GSoC, I'm an Electronics enthusiast and have a great interest in fields like FPGA, Digital VLSI, Computer Architecture. I have Experienced with Altera, Sipeed, and Lattice FPGAs. I like the beaglewire GSoC Idea and it will be a pleasure to contribute to it
About your project
Project name: Beaglewire Software Support
Description
In 10-20 sentences, what are you making, for whom, why and with what technologies (programming languages, etc.)? (We are looking for open source SOFTWARE submissions.)
- Introduction
Beagle Wire is an FPGA Cape for the beaglebone black. In this project, I'm developing and testing the existing software support of Beaglewire. The known primary issue in Beaglewire is the interface between 32MB SDRAM and ICE40HX4K. For this Solution, I'm going to try LiteDRAM(a small footprint and configurable DRAM core). There are two grove Connectors on BeagleWire for I2C, I'm going to found whether there is improvement needed in the existing I2C Verilog code and will also provide some example code with simple I2C sensors.
I will also test Subsystems like PWM, UART in actual hardware, if found not working will correct the subsystems and provide appropriate examples codes for them.
Timeline
Provide a development timeline with a milestone each of the 11 weeks and any pre-work. (A realistic timeline is critical to our selection process.)
| Mar 30 | Proposal complete, Submitted to https://summerofcode.withgoogle.com |
| Apr 27 | Proposal accepted or rejected |
| May 18 | Pre-work complete, Coding officially begins! |
| May 25 | Milestone #1, Introductory YouTube video |
| June 1 | Milestone #2 |
| June 8 | Milestone #3 |
| June 15 18:00 UTC | Milestone #4, Mentors and students can begin submitting Phase 1 evaluations |
| June 19 18:00 UTC | Phase 1 Evaluation deadline |
| June 22 | Milestone #5 |
| June 29 | Milestone #6 |
| July 6 | Milestone #7 |
| July 13 18:00 UTC | Milestone #8, Mentors and students can begin submitting Phase 2 evaluations |
| July 17 18:00 UTC | Phase 2 Evaluation deadline |
| July 20 | Milestone #9 |
| July 27 | Milestone #10 |
| August 3 | Milestone #11, Completion YouTube video |
| August 10 - 17 18:00 UTC | Final week: Students submit their final work product and their final mentor evaluation |
| August 17 - 24 18:00 UTC | Mentors submit final student evaluations |
Experience and approach
In 5-15 sentences, convince us you will be able to successfully complete your project in the timeline you have described.
Contingency
What will you do if you get stuck on your project and your mentor isn’t around?
Benefit
If successfully completed, what will its impact be on the BeagleBoard.org community? Include quotes from BeagleBoard.org community members who can be found on http://beagleboard.org/discuss and http://bbb.io/gsocchat.
Misc
Please complete the requirements listed on the ideas page. Provide link to pull request.
Suggestions
Is there anything else we should have asked you?
