BeagleBoard/GSoC/2021 Proposal/OmkarBhilare

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Proposal for Beaglewire Software Support

About Student: Omkar Bhilare
Mentors: Michael Welling
Code: gsoc-application
GSoC: GSoC entry


This project is currently just a proposal.


Completed All the requirements listed on the ideas page.
The PR request for cross-compilation task: #154.

About you

IRC: Omkar Bhilare
Github: ombhilare999
School: Veermata Jijabai Technological Institute
Country: India
Primary language : English, Hindi, Marathi
Typical work hours: 10AM-8PM Indian Standard Time
Previous GSoC participation: This is my first time applying for GSoC, I'm an Electronics enthusiast and have a great interest in fields like FPGA, Digital VLSI, Computer Architecture. I have experienced with Intel's Quartus, Xilinx's vivado, and opensource toolchains for ice40. I have also experience with Cyclone2, Upduino3.0(ICE40), Sipeed Tang Primer FPGA.

About your project

Project name: Beaglewire Software Support



The BeagleWire is an FPGA development platform that has been designed for use with BeagleBone boards. BeagleWire is a cape on which there is an FPGA device - Lattice iCE40HX. The software support for BeagleWire is still in the development phase. In this project, I'm developing and testing the existing software support of Beaglewire. The known primary issue in Beaglewire is the interface between 32MB SDRAM and ICE40HX4K. For this Solution, I'm going to try LiteDRAM(a small footprint and configurable DRAM core).

Why LiteDRAM for SDRAM Control

The Core produced by LiteDRAM is
1. Fully pipelined, high performance.
2. Configurable commands depth on bankmachines.
3. Auto-Precharge.
4. Periodic refresh/ZQ short calibration (up to 8 postponed refreshes).

LiteDRAM is already used in commercial and open-source designs
Testing of I2C, SPI, PWM, UART

There are two grove Connectors on BeagleWire for I2C, I will test the current Verilog Code of I2C in hardware and will find out whether there is improvement requirement in I2C or not.
I will also test Subsystems like PWM, UART in actual hardware, if found not working will correct the subsystems and provide appropriate examples codes for them.


Provide a development timeline with a milestone each of the 11 weeks and any pre-work. (A realistic timeline is critical to our selection process.)

Mar 30 Proposal complete, Submitted to
Apr 27 Proposal accepted or rejected
May 18 Pre-work complete, Coding officially begins!
May 25 Milestone #1, Introductory YouTube video
June 1 Milestone #2
June 8 Milestone #3
June 15 18:00 UTC Milestone #4, Mentors and students can begin submitting Phase 1 evaluations
June 19 18:00 UTC Phase 1 Evaluation deadline
June 22 Milestone #5
June 29 Milestone #6
July 6 Milestone #7
July 13 18:00 UTC Milestone #8, Mentors and students can begin submitting Phase 2 evaluations
July 17 18:00 UTC Phase 2 Evaluation deadline
July 20 Milestone #9
July 27 Milestone #10
August 3 Milestone #11, Completion YouTube video
August 10 - 17 18:00 UTC Final week: Students submit their final work product and their final mentor evaluation
August 17 - 24 18:00 UTC Mentors submit final student evaluations

Experience and approach

In 5-15 sentences, convince us you will be able to successfully complete your project in the timeline you have described.


What will you do if you get stuck on your project and your mentor isn’t around?


If successfully completed, what will its impact be on the community? Include quotes from community members who can be found on and


Please complete the requirements listed on the ideas page. Provide link to pull request.


Is there anything else we should have asked you?