Difference between revisions of "BeagleBoard/GSoC/2022 Proposal/TaliaXu"

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==About your project==
 
==About your project==
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''Project name'': RISC-V Based PRU on FPGA and Beglewire Updates<br>
  
 
===Timeline===
 
===Timeline===

Revision as of 13:01, 30 March 2022

Proposal for Beaglewire PRU and Support

About Student: Talia Xu
Mentors: Michael Welling, Bhilare
Proposal:Xu BeagleWire Software

Proposal

  • Completed All the requirements listed on the ideas page.
  • The PR request for cross-compilation task: #162.

Status

This project is currently just a proposal.

About you

Github: taliaxu09
School: [Technical University of Delt]
Country: The Netherlands
Primary language : English
Typical work hours: 12PM-8PM European Central Time
Previous GSoC participation: This is my first time applying to participate for GSoC. I want to patricipate in GSoC with BeagleBoard because I think this is a great opportunity to gain a deeper knowledge of the code repository of BeagleBoard and explore how to use it together with different peripherals. I also think the BeagleWire could be a promising candidate for some of the topics I wish to look into in my study on visible light communication.


About your project

Project name: RISC-V Based PRU on FPGA and Beglewire Updates

Timeline

Date Status Details
Presubmission
  • Build a BeagleWire image & install toolchain (completed)
  • Verify that I am able to edit, recompile and program the FPGA (completed)
May 20th - June 12th Community Bonding
  • Define the exact scope of the project before the end of this period (PolarFire Vs. ICE40 implementation & draw out specifications for I/O latency)
  • Read about PRU documentation, and run PRU examples on BBB and Litex
  • Read about the RISC-V implementation on Silice
  • Introduction Video
June 13th Milestone #1
  • Implement Neorv and serv on BeagleWire
June 20th Milestone #2
  • Document the process with a blog post
  • Evaluate the I/O latency using an oscilloscope
  • Look into the generated hardware blocks to identify the blocks with highest delays and look for ways to overcome the,
June 27th Milestone #3
  • Implement multiple RISC cores and generate examples with peripherals running on the cores
  • Look into the space usage, optize it (if needed) to fit multiple cores
July 4th Milestone #4
  • Implement multiple PWMs, low latency examples
  • Implement an example running both PRUs on FPGA and PRUs on BBB
July 11th Milestone #5
  • Implement other examples (soft UARTs, low-latency IOs)
July 18th Milestone #6
  • Demonstration of multiple peripherals running on separate cores at the same time
  • Prepare a report summarizing progress with the PRU cores
July 25th Milestone #7
  • Read about the previous open issues on standalone cores
  • Look into reproducing #7, #8 SDRAM issues with the standalone core
  • Try to reproduce the error with standalone SDRAM with a test scrips
August 1st Milestone #8
  • Look into the verilog code and timing reports to figure out errors on SDRAM
August 8th Milestone #9
  • Implement automated test script for different subsystems (SPI, PWM, UART)
August 15th Milestone #10
  • Look into the verilog code and timing reports to see if there is anything wrong with the different subsystems
August 22nd Milestone #11
  • Read on nMigen support if there is time, otherwise budgeting the week for overflow
August 29th Milestone #12
  • Submit final work product and final mentor evaluation
  • Complete YouTube video
Sep. 5th Milestone #13
  • Completion of GSoC