Difference between revisions of "BeagleBone Power Management"

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m (Power supplies)
m (Power supplies)
Line 24: Line 24:
| LDO2 || 3.3 V || align=right|100 mA || power led
| LDO2 || 3.3 V || align=right|100 mA || power led
| LDO2 || 3.3 V || align=right|100 mA || power led
| LDO2 || 3.3 V || align=right|100 mA || power led (3v3aux)
| LDO3 || 3.3 V || align=right|200 mA || 3v3a
| LDO3 || 3.3 V || align=right|200 mA || 3v3a

Revision as of 19:56, 28 May 2015

Work in progress: plan is to first collect the raw info, then organize and add prose.

Power supplies

Main voltage regulators (supplied by SYS)
BBone White (TPS65217B) BBone Black (TPS65217C)
LDO1 1.8 V 100 mA vrtc LDO1 1.8 V 100 mA vrtc
DCDC1 1.8 V 1200 mA ddr2 DCDC1 1.35 V 1200 mA ddr3l
1v8 LDO3 1.8 V 400 mA 1v8
LDO2 3.3 V 100 mA power led LDO2 3.3 V 100 mA power led (3v3aux)
LDO3 3.3 V 200 mA 3v3a LDO3 3.3 V 400 mA 3v3a
LDO4 3.3 V 200 mA 3v3b U4 3.3 V 500 mA 3v3b
U8 3.3 V 1000 mA 3v3exp 3v3exp
DCDC2 1.285 V 1200 mA vdd_mpu DCDC2 1.325 V 1200 mA vdd_mpu
DCDC3 1.125 V 1200 mA vdd_core DCDC3 1.125 V 1200 mA vdd_core

Note 1: The TPS65217C configures DCDC1 at 1.5V by default (for DDR3). For the BBB, this is changed to 1.35V (for DDR3L) by software before RAM is released from reset.

Note 2: This shows DCDC2/3 voltage levels after software reconfiguration for maximum performance. Initial voltage levels are 1.1V for both.

Considerations for external connections

Most pins on the expansion headers are directly connected to processor I/O pins, which are supplied by the 3v3a (for drivers, pull-ups, and protection diodes). While power-on-reset is asserted (PGOOD low) these are never driven by the processor but have a (weak) pull-up/down enabled (default pull-direction varies per pin). External hardware must refrain from driving these pins unless the 3v3a has stable power. Unfortunately, neither the 3v3a nor PGOOD is available on the expansion headers, however the following relationships can be used:

  • if 3v3a is not powered, PGOOD will be low;
  • if PGOOD is low, nRESET will be low (since BBB rev A6) or pulled to 3v3a (before)
  • if 3v3a is powered, 3v3exp will also be powered.

Therefore external hardware can abide by the rules by

  • accepting the possibility that pins may be driven by the processor when 3v3exp is powered, and
  • refraining from driving processor pins when 3v3exp is unpowered or nRESET is low.

These criteria are met for example by powering logic from 3v3exp but making sure its drivers are disabled while nRESET is low.

Power down

Hardware is a BBB rev C patched to have a unified 3v3 rail, no external connections other than power, probes, and console cable.

Two kernels are compared: the one on the right is a standard kernel + device tree which enables the (reset-insensitive) HDMI framer, while the one on the left leaves the HDMI framer in standby (its default state, negligible power consumption). There are other differences, but those should be irrelevant during shutdown, certainly once power-on reset is asserted (PGOOD low).

Clean shutdown while powered via BAT:
Bbb-c-3v3u-shutdown-bat5v.png Bbb-c-3v3u-shutdown-bat5v-hdmi.png

Most current consumption is eliminated at the start of the powerdown sequence when PGOOD goes low, although there's a brief burst shortly afterwards (no idea why). Current ramps down more 2 ms later when the core and mpu supplies are disabled, and drops to negligible once the 3v3 supply is cut. Current temporarily increases again due to VDDS leakage until it too is cut.

When the HDMI framer is enabled, its continued current consumption (until 1v8 is cut) is clearly visible.

Clean shutdown (while powered via DC plug):
Bbb-c-3v3u-shutdown-dc5v.png Bbb-c-3v3u-shutdown-dc5v-hdmi.png

Same thing, but with the power path being cut by the PMIC at the start of the powerdown sequence, the BeagleBone is now running off its capacitors. In this case it managed to make it without losing regulation at any point, but only barely so. With the HDMI framer enabled the 3v3 and 1v8 supplies receive a premature dent.

Undervoltage shutdown due to (very slow) supply ramp-down:
Bbb-c-3v3u-rampdown-dc.png Bbb-c-3v3u-rampdown-dc-hdmi.png

The PMIC tries, it really does. In fact, while the 3.3V supplies can't be saved (obviously, with the SYS capacitors charged at a mere 3.4V or so), when not burdened by the HDMI framer it still has 2.4V on SYS by the time the 3v3 is disabled, so it almost certainly would have maintained regulation on the remaining supplies if the VDDS leakage hadn't ruined it.

Power cut abruptly:
Bbb-c-3v3u-powercut.png Bbb-c-3v3u-powercut-hdmi.png

By the time the PMIC intervenes the 3v3 supply has already lost regulation, and it clearly makes no attempt to sequence the remaining supplies but disables them simultaneously. The HDMI kernel actually initially has a gentler slope since that kernel happens to have better power management. The inexplicable sudden steepening of slope that happens there is worrying.