CI20 Hardware

This page details the technical specifications and components of the MIPS Creator CI20 development board.

Tech Spec overview

Feature	Details
SoC	Ingenic JZ4780
CPU	Dual 1.2GHz XBurst MIPS32 little endian
Caches	32kI + 32kD per core, 512K shared L2
RAM	1Gbyte DDR3
NAND	8 Gbyte
SDcard	1x full size slot + 1x slot via secondary expansion header
USB	1x USB otg + 1x USB host
Ethernet	1x 10/100Mbps using Davicom DM9000C controller over 8-bit interface
Wifi	IW8103 wifi-? + BT4, built in ceramic aerial
GPU	PowerVR SGX540
Video	Hardware video decoder up to 1080p60
Display	HDMI, up to 2k resolution
Camera	ITU645 dedicated connector
GPIO	25 available on headers
SPI	2 ports on primary & secondary expansion header, with 4 chip selects
I2C	One port on primary expansion header
ADC	7 inputs on secondary expansion header, including 5-wire touch and battery monitoring functions
UART	1 on dedicated UART header, 2 via primary expansion header
Audio	Audio in and out via 3.5mm 4-wire connector
JTAG	Standard 14-pin MIPS EJTAG header
Transport Stream Interface	Via secondary expansion header
Power	5V via 4mm (shield) x 1.7mm (pin) center positive connector
Size	Approx 90x95mm

Connectors

Connector	Schem Name	Details
Power	MK5	4mm shield x 1.7mm pin 5V centre positive
HDMI	J3	Full size HDMI out, including audio support
USB A connector (left)	J24	Paralleled with the mini OTG connector (note, they are not separate ports - do not plug into both at once!)
USB A connector (right)	J23	From the EHCI host controller block
USB mini-OTG connector	J8	Paralleled with the full size A connector next to it.
OTG VBUS jumper	JP2	Selects VBUS enabling on OTG port to enable master or slave functionality
Ethernet	J11	Standard RJ45 connector, with built in link and activity lights
Audio	J9	3.5mm 4-pin (stereo out + mic in), with auto-sense chip to handle both OMTP and CTIA headsets
Button	SW1	Boot time selector (see boot selector table). Can also be read from software as GPIO. Note, this is not a reset button!
Boot mode selector	JP3	Used to choose auto-boot from NAND or SDcard slot, predominantly.
SDcard	J13	Full size SDcard slot, can be used for storage and/or direct boot
Camera	J6	24-pin DVP camera connector
IR	U15	Infrared receiver
LED	D5	bi-colour status LED (red/blue), wired to USB power enable line
UART	J57	Dedicated 4-pin UART header
Primary expansion connector	JP4	26-pin (2x13) 'RPi compatible' 0.1" pitch expansion connector, carrying power, UART, SynchronousSerial, I2C and GPIO functions.
Secondary expansion header	J5	Carries 5v and 3.3v power out, transport stream, ADC, GPIO, SynchronousSerial(SPI) and MSC(SDcard) functions
EJTAG	J58	Standard MIPS 14pin EJTAG connector

Power

The power connector is a 5V 4mm (shield) x 1.7mm (pin) center positive connector. It takes 5V only. Note that this connection is identical to that of the original Sony PSP, so power cables intended for that console also work for the CI20.

State	Current draw @ 5V
Power off	0 mA
Suspended	30 mA
Idle (no devices plugged in, Wi-Fi off)	210 mA
Maximum usage (Ethernet, Wi-Fi, SDcard, CPU, GPU all stressed)	750 - 800 mA

Device	Current draw @ 5V
HDMI	trace
Wi-Fi - in use	100 mA
Wi-Fi - idle	trace with spikes of around 40 mA
Ethernet - in use	150 mA
Ethernet - idle	120 mA
CPU + Memory - in use (compared to idle)	90 mA
SDCard - writing	90 mA
SDCard - reading	60 mA

HDMI

Full sized HDMI connection with audio out support as well. The HDMI block on the JZ4780 supports HDMI v1.4a.

USB A connector (left)

Paralleled with the mini-OTG connector.

USB A connector (right)

Connected to the EHCI USB controller in the SoC.

USB mini-OTG connector

Is paralleled with the left hand USB A connector - do not plug into both of these at once. Has the OTG VBUS controlled by the jumper next to it.

OTG VBUS jumper

Controls the VBUS for the OTG ports-

Jumper shorted = HOST mode.

Jumper not shorted = Device mode.

Ethernet

10/100 RJ45, connects to the DM9000 chipset.

Audio

Standard 4-pin headset connector, with auto OMTP/CTIA detection (so should work with any standard 4-pin headset).

Button

The button between HDMI and Ethernet is not a reset button.

It is boot_select0. Combined with JP3, it can be used to boot the CI20 from the USB.

It can also be used as a gpio once the CI20 is powered up. The boot_sel0 pin is connected to PD17.

Pinmux options can be checked to see which gpio is PD17 in kernel you booted.

In the 3.15 kernel, the gpio is number 113.

You can export the gpio via

echo 113 > /sys/class/gpio/export

And then use it.

Boot mode selector

See the silkscreen on the board and the section at the end of the JZ4780 programmers manual. Fundamentally you can boot from the on-board NAND or direct off the SDcard without having to press the button during boot. There is also a USB boot function available, but it is not a standard DFU type boot, and requires JZ4780 specific host support.

BOOT_SEL[2:1:0]	JP3 Jumper (BOOT_SEL1, PD18)	SW1 Button (BOOT_SEL0, PD17)	Boot Mode
110	Pins 1 & 2 shorted	Not pressed	NAND flash at CS1
100	Pins 2 & 3 shorted	Not pressed	SD Card at MSC1
111	Pins 1 & 2 shorted	Pressed	USB device
101	Pins 2 & 3 shorted	Pressed	tSD NAND flash at MSC0

SDcard

Standard pinout full sized SD/MMC slot. Can be used for direct booting, or for bulk storage (standard MTD support under Linux). Is wired to the MSC0 block in the SoC.

Camera

Closeup of compatible camera

Closeup of back of compatible camera

Camera unit fitted

The camera connector is 24 pin (26 pins on the schematic - two of which are the side ground solder tabs on the connector itself - the actual cable interface is 24 pin), and CMOS DVP 8-bit camera compatible.

The Omnivision OV5640 5Mpixel unit can be used with the CI20 (often labelled FD5640 on the actual part)

The connector installed on the CI20 is 24-PIN 0.5Pitch Bottom Contact FPC Connector

A camera module reported to be working by a community member here

Note Be aware that there are some SMT components directly under where the camera unit sits. If your camera unit has a conductive rear surface then this may short out on the board. Symptoms we have seen include board resets. Please insulate the area either on the PCB or the back of the camera unit to avoid this.

IR

The CI20 has an infrared remote control receiver (part IRM-2638A, carrier frequency 37.9kHz), which is connected to GPIO PE3 for software decoding.

LED

The CI20 board features a dual colour red & blue LED. It is controlled by GPIO PF15, which also controls the USB VBUS supply. When PF15 is high the LED lights red, when PF15 is low it lights blue. Software cannot power off the LED. A simple way to toggle the LED colour is to write to the PFPAT0S & PFPAT0C registers from the U-boot shell, in order to toggle the PF15 GPIO. The following example will toggle the colours rapidly, leading to the LED appearing purple:

while true; do mw.l 0xb0010548 0x8000; mw.l 0xb0010544 0x8000; done

Dedicated UART header

Pinout and other functions of the dedicated UART header. This is uart4 of the SoC. Note that uart0 is on the 26pin main expansion header.

pin	schematic	GPIO	2nd func	3rd func
1	+3v3
2	TXD	PC10	LCD_SPL	LCD_G0
3	GND
4	RXD	PC20	LCD_CLS	LCD_R0

Key	Power	UART4	GPIO	LCD

Primary expansion header

Pinout diagram for the main CI20 0.1" pitch 26 pin header

2nd func	GPIO	schematic	pin	pin	schematic	GPIO	2nd func	3rd func	4th func
		+3v3	1	2	5V_IN
	PD30	I2C1_SDA	3	4	5V_IN
	PD31	I2C1_SCK	5	6	GND
UART1_TXD	PD28	GPIO1	7	8	UART0_TXD	PF3
		GND	9	10	UART0_RXD	PF0	GPS_CLK
UART1_RXD	PD26	GPIO2	11	12	PWM	PF5	PWM5	UART3_TXD	SCLK_RSTN
UART1_CTS	PD27	GPIO3	13	14	GND
UART1_RTS	PD29	GPIO4	15	16	GPIO5	PF1	UART0_CTS	GPS_MAG
		+3v3	17	18	GPIO6	PF2	UART0_RTS	GPS_SIG
SSI1_DT	PE17	SSI0_DT	19	20	GND
SSI1_DR	PE14	SSI0_DR	21	22	GPIO7	PE8	UART3_CTS	BCLK_AD
SSI1_CLK	PE15	SSI0_CLK	23	24	SSI0_CE0	PE16	SSI1_CE0
		GND	25	26	SSI0_CE1	PE18	SSI1_CE1

Key	Power	UART0	UART1	UART3	SSI
	GPS	I2C	I2S	GPIO	PWM

1. Note that the PWM facility is unavailable as this PWM unit is used by the Linux kernel SMP timer code
2. Note that the GPS interface is unavailable as it is (believed to be) electrically incompliant
3. Note that the I2S block is not useable on the header as not all I2S pins are brought out

Secondary expansion header

Pinout diagram for the secondary CI20 0.1" pitch 16 pin header

3nd func	2nd func	GPIO	schematic	pin	pin	schematic	GPIO	2nd func	3rd func
			+3v3	1	2	5V_IN
TSFRM	MSC2_D3	PB31	SSI1_CE0	3	4	SSI1_CLK	PB28	MSC2_CLK	TSCLK
TSSTR	MSC2_CMI	PB29	SSI1_DT	5	6	SSI1_DR	PB20	MSC2_D0	TSDIO
TSDI1	MSC2_D1	PB21	SSI1_CE1	7	8	SSI1_GPC	PB30	MSC2_D2	TSFAIL
			XP	9	10	XN
			YP	11	12	YN
			AUX1	13	14	AUX2
			VBAT	15	16	GND

Key	Power	TSSI	ADC	GPIO	SSI	MSC

EJTAG

14-pin MIPS EJTAG headers. See proposed OpenOCD/wiggler support project.

3nd func	2nd func	schematic	pin	pin	schematic
		TRST_N	1	2	GND
PS2_KCLK	UART3_RXD	TDI_RXD	3	4	GND
PS2_KDATA	UART3_TXD	TDO_TXD	5	6	GND
PS2_MDATA	UART3_CTS	TMS	7	8	GND
PS2_MCLK	UART3_RTS	TCK	9	10	GND
		RST_N	11	12	N/C
		N/C	13	14	3V3

Key	Power	PS2	UART3	EJTAG

1. Note that the JTAG function is controlled by PA30, and may be turned on by the bootloader - see the JZ4780 Programmers Manual

Components

SoC

Is an Ingenic JZ4780 - see the data sheet and programmers manuals referenced on this page.

DDR/RAM

Comprises of four H5TQ2G83DFR-H9C 2Gbit DDR3 chips, providing 8 bits of data each, providing a 32bit DDR3 memory bus to the SoC. Anybody have details of the standard clock rate?

ROM/NAND

Is provided by a single Samsung K9GBG08UOA NAND flash, using an 8bit data interface to the SoC.

Ethernet

Is provided by a Davicom DM9000C connected vi an 8-bit interface to the SoC, providing 10/100 ethernet.

WiFi/BT

Is provided by an Ingenic IW8103, based on a Broadcom 4330, connected via SDIO to the SoC MSC1 port.

PMU

Is an Active-Semi ACT8600 specifically designed for the Ingenic JZ family of SoCs.

RTC

Is provided by a Pericom PT7C4337UE connected to the SoC via the I2C_4 bus.

Microphone switcher

The automatic 4-pin microphone switching/detection is provided by a Fairchild FSA8049 audio jack detection device.

Test Points

Description of the (rather small little silver dot) test points on the board, derived from the schematic.

Label	Function
TP9	LCD PCLK output
TP72	TEST_TE input
TP10	DRVVBUS
TP8	CLK32K
TP19	BOOT_SEL2 boot mode setting - pulled high to 3.3V with a 10K resistor.
TP20	BOOT_SEL1 boot mode setting - shared with JP3 (the boot mode jumper)
TP21	BOOT_SEL0 boot mode setting - shared with SW1 (the button)
TP24	VDDMEM
TP25	VDDCORE
TP26	+3.3V rail
TP27	+2.5V rail
TP23	VRTC18/WKUP_N through 100K resistor
TP22	VRTC18/RST_N through 200K resistor
TP62	DEVICE_VBUS
TP63	OTG_DM
TP64	OTG_DP
TP65	Ground
TP66	HOST_5V
TP67	USB_DM
TP68	USB_DP
TP69	Ground
TP77	WIFI_IO
TP136	Wifi chip RF_SW_CTRL_3 pin
TP137	Wifi chip RF_SW_CTRL_6 pin

Documentation

The following links provide information (predominantly PDF files) about the SoC, board and components for the MIPS Creator CI20.

SoC Information

Overview on the Imagination web site

JZ4780 pdf datasheet from the Ingenic FTP site

Programmers Manual

JZ4780 pdf programmers manual from vendor file archive

Schematic

Schematic for V1 boards is available here. And for V2 boards here

Board components and identification

Board/component (BOM) identification pdf from the CI20 file archive

DDR chip manual CI20 file archive

Davicom DM9000C Ethernet controller device datasheet

NAND chip manual CI20 file archive

Power Management Unit (PMU) chip manual CI20 file archive

Real Time Clock (RTC) chip manual CI20 file archive

Expander pinouts

Main expander pinout and function diagram pdf from the CI20 file archive (also on Hardware page)

Secondary expander pinout and function diagram pdf from the CI20 file archive (also on Hardware page)

Dedicated UART header pinout and function diagram pdf from the CI20 file archive (also on Hardware page)

EJTAG header pinout and function digram on Hardware page

OTP and MAC address formats

The following data is stored in the JZ4780 OTP ROM/efuse. This data can be accessed from Linux via the sysfs path of

/sys/devices/platform/jz4780-efuse/

The C definition of the actual efuse area data format is:

struct __packed__ otp {
    uint32 serial_number;  /* As a decimal, huge range */
    uint32 date; /* ISO8601 yyyymmdd format-ish as an int – for instance ‘20140527’d for May 27th 2014 */
    char manufacturer[2];  /* ascii 2-character encoding of manufacturer – ‘NP’ == Nopa */
    unsigned char mac[6]; /* six byte/48bit MAC address stored as 8-bit integers */
};