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For more interesting projects done by Flameman, be sure to checkout his project index


The board has been made be synergy microsystem as V462 (dual processor) in V460 Series It seems the board+bsp+vxworks has been sold as "EUROCOM 27xxx"


  • CPU: dual 33 MHz 68060 processors
  • ram: 64 Mbytes, DRAM
  • lan: Ethernet
  • interface: Graphics, SCSI-2, VME 32/64?
  • OS: comes with OS-9, LynxOS, pSOS+, PDOS, VxWorks


  • Memory is provided on a piggyback module allowing it to be easily upgraded
  • Up to 4 Mbytes of FLASH
  • Supports ELTEC's LEB mezzanine bus

Working scheme

is this system (hw-2x68060/vxworks)s.m.p. or a.m.p. ?

it seems that the dual-CPU V460 is featuring a symmetrical architecture allowing the two 68060 CPUs to operate as either tightly-coupled coprocessors sharing the same operating system and peripherals or as two independent CPUs running separate operating systems across separate I/O channels.


If this info is right it should be possible to assign different interrupt level schemes to each CPU via a programmable interrupt control register. In all of these possible arrangements, the dual CPU V460 Series can provide full multi-ported memory access by both CPUs, the VMEbus, and both EZ-bus modules with varying levels of memory protection as required.

power needed

V460 model (50 MHz, 8 MB RAM)

  • +5.0v ±5% = 6.4 amps (typical)
  • -12.0v ±5% = 30 mA

vme backplane


VMEbus connector pinouts VMEbus P1 VMEbus P2

Pin Row A Row B Row C Pin Row A * Row B Row C** 
1 D00 BBsy\ D08 1 P4 - pin B32 +5v P4 - pin A32 
2 D01 BClr\ D09 2 P4 - pin B31 Gnd P4 - pin A31 
3 D02 ACFail\ D10 3 P4 - pin B30 reserved P4 - pin A30 
4 D03 BG0In\ D11 4 P4 - pin B29 A24 P4 - pin A29 
5 D04 BG0Out\ D12 5 P4 - pin B28 A25 P4 - pin A28 
6 D05 BG1In\ D13 6 P4 - pin B27 A26 P4 - pin A27 
7 D06 BG1Out\ D14 7 P4 - pin B26 A27 P4 - pin A26 
8 D07 BG2In\ D15 8 P4 - pin B25 A28 P4 - pin A25 
9 Gnd BG2Out\ Gnd 9 P4 - pin B24 A29 P4 - pin A24 
10 SysClk BG3In\ Sysfail\ 10 P4 - pin B23 A30 P4 - pin A23 
11 Gnd BG3Out\ BErr\ 11 P4 - pin B22 A31 P4 - pin A22 
12 DS1\ BR0\ SysRes\ 12 P4 - pin B21 Gnd P4 - pin A21 
13 DS0\ BR1\ LWord\ 13 P4 - pin B20 +5v P4 - pin A20 
14 Write\ BR2\ AM5 14 P4 - pin B19 D16 P4 - pin A19 
15 Gnd BR3\ A23 15 P4 - pin B18 D17 P4 - pin A18 
16 DTAck\ AM0 A22 16 P4 - pin B17 D18 P4 - pin A17 
17 Gnd AM1 A21 17 P4 - pin B16 D19 P4 - pin A16 
18 AS\ AM2 A20 18 P4 - pin B15 D20 P4 - pin A15 
19 Gnd AM3 A19 19 P4 - pin B14 D21 P4 - pin A14 
20 IAck\ Gnd A18 20 P4 - pin B13 D22 P4 - pin A13 
21 IAckIn\ SerClk(1) A17 21 P4 - pin B12 D23 P4 - pin A12 
22 IAckOut\ SerDat\(1) A16 22 P4 - pin B11 Gnd P4 - pin A11 
23 AM4 Gnd A15 23 P4 - pin B10 D24 P4 - pin A10 
24 A07 IRQ7\ A14 24 P4 - pin B9 D25 P4 - pin A9 
25 A06 IRQ6\ A13 25 P4 - pin B8 D26 P4 - pin A8 
26 A05 IRQ5\ A12 26 P4 - pin B7 D27 P4 - pin A7 
27 A04 IRQ4\ A11 27 P4 - pin B6 D28 P4 - pin A6 
28 A03 IRQ3\ A10 28 P4 - pin B5 D29 P4 - pin A5 
29 A02 IRQ2\ A09 29 P4 - pin B4 D30 P4 - pin A4 
30 A01 IRQ1\ A08 30 P4 - pin B3 D31 P4 - pin A3 
31 -12v +5vStdby +12v 31 P4 - pin B2 Gnd P4 - pin A2 
32 +5v +5v +5v 32 P4 - pin B1 +5v P4 - pin A1 

Notes: * This row of pins on P2 connect to the pin listed in row B of the EZ-bus connector (P4).

         ** This row of pins on P2 connect to the pin listed in row A of the EZ-bus connector (P4).


Pin row B of the P2 backplane is defined 
by VMEbus specifications and is bussed 
across the entire backplane. Pin rows A 
and C are user configured and, if con– 
nected at all, are normally connected to 
adjacent slots via wirewrap or special ca- 
Because the P2 pinout may vary between 
backplanes or even slots in the same 
backplane, DO NOT INSTALL the V460 
Series  into a system  slot whose P2 
backplane is not compatible with the 
V460 Series’ P2 pin-out. Failure to 
observe this warning can cause the 
complete destruction of many on-board 
components and also voids the product 
The V460 Series pin-out meets standard 
VME specifications for row B, but rows A 
and C will vary according to the EZ-bus 
daughter module installed. Daughter 
board pinouts are shown in the 
associated daughter module manual. If 
no daughter module is present, P2 back- 
plane rows A and C are defined as no- 
For a complete list of the V460 Series P2 
assignments, see the VMEbus connectors 
(P1-P2) chapter in Section 7. 


On V460 Series dual-68060 models, the following boot architecture is used:

  • CPU-X executes from EPROM0 at 0xFE000000 to 0xFE0FFFFF
  • CPU-Y executes from EPROM1 at 0xFE400000 to 0xFE4FFFFF or 0xFD000000 to 0xFDFFFFFF

except for the first 3 fetches in boot state in which CPU-X fetches from PROM0 and CPU-Y fetches from PROM1 either 68060 can execute from either or both of the EPROMs.