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− | amcc/ibm walnut ppc405gp
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− | = walnut - IBM PPC405GP EVB =
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− |
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− | == Overview ==
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− |
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− | The board consists of:
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− |
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− | * '''CPU''' PowerPC 405GP running at 200Mhz
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− | * '''RAM''' PC133 SDRAM slot, currently, only supports single sidded DIMMs
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− | * '''LAN''' On-chip 405GP ethernet, board doesn't have an ethernet MAC address (the monitor/bootloader is able to fix it)
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− | * '''UART''' 2xDCE serial port, speeds up to 230k, only tested to 115200bps
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− | * '''PCI''' for pci slots, keyed for 5V only cards
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− | * '''ROM''' 512k of boot flash, AMD 29LV040B (amd29lv040b.pdf), socketed
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− | * '''POWER''' the board need ATX power
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− | * '''System PCB ''' ATX board size, 310x250mm
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− | * '''RTC''' the real time clock chip is??? there ia chip but dunno about
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− | * '''RAM''' 128M PC133 SDRAM DIMM
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− | * '''FIRMWARE''' ibm-evb-mon (horrible), it has been replaced by uboot
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− |
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− | == cpu ==
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− |
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− | A fast, flexible solution for embedded developers.
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− |
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− | General Description
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− | The AMCC PowerPC 405GP and 405GPr family of 32-bit RISC processors is designed to provide a flexible, fast time-to- market hardware solution to satisfy the demands of high-performance embedded applications. Implemented in the scalable PowerPC architecture, the 405GP and 405GPr processors maintain code compatibility with other PowerPC processors for ease in migration and faster time-to-market. An optimized balance of performance, low power, and features makes them ideal solutions for communication, data storage, and pervasive computing applications.
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− |
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− | The 405GP and 405GPr processors support speeds of up to 266MHz and 400MHz respectively. Both incorporate a rich mix of features, such as a PCI interface, an SDRAM Controller, a 64-bit on-chip CoreConnect bus, Ethernet and other on-chip peripheral support, and the IBM CodePack™ code compression engine. In addition, power management features, a small form factor, and low power consumption make the AMCC 405 processor family an ideal platform for applications ranging from networking to video.
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− |
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− | Highlights
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− |
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− | * High-performance, low-power processors for the most demanding embedded applicationsPowerPC 405GP/405GPr Embedded Processors deliver up to 400MHz performance and a rich mix of features for Internet, communication, data storage, consumer, and imaging applications
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− | * Includes on-chip SRAM with single-cycle access for faster processing in data-intensive applications, such as routers and switches
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− | * Supports full application-code compatibility with all other PowerPC® processors for seamless migration
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− | * Uses the award-winning 64-bit IBM CoreConnect™ high-performance on-chip bus
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− | * Offers a wide array of small-footprint- package options for high-density applications, such as telecommunications devices
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− | * Employs the IBM CodePack™ code compression core to reduce system memory requirements and cost
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− |
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− | Features
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− |
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− | * On-chip SDRAM Controller
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− | o Contains separate 32-byte read and 128-byte write buffers
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− | o Programmable address mapping
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− | * External Peripheral Controller
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− | o Supports ROM, EPROM, SRAM
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− | o Flash and slave peripheral I/O devices
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− | o 8-, 16-, 32-bit external data bus width
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− | o Programmable address mapping
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− | * External Bus Master Controller - Allows external masters to access SDRAM and PCI
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− | * DMA Controller
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− | o 4 independent channels
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− | o Supports transfers between SDRAM, PCI, internal UARTs, and devices on the external peripheral bus
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− | * PCI Interface
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− | o 32-bit PCI V2.2 compatible
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− | o Synchronous and asynchronous operation
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− | o Internal PCI arbiter supports six PCI masters
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− | o Supports external arbitration
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− | * On-chip Ethernet Support
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− | o 10/100 MAC
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− | o Dedicated DMA controller
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− | * CodePack Decompression
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− | o Stores instructions in memory in compressed format
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− | o Improves code density by up to 40%
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− | * Other On-chip Peripherals
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− | o 2 serial ports
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− | o Master and slave IIC controller
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− | o Up to 24 general purpose I/Os
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− | o Interrupt controller including up to 13 external interrupts
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− |
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− |
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− |
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− |
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− | == WindRiver VxWorks ==
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− |
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− | <pre>
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− | walnut_target(1)
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− |
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− |
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− | walnut - IBM PPC405GP EVB
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− |
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− |
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− |
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− | IBM PPC405GP EVB
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− |
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− | INTRODUCTION
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− |
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− | This reference entry provides board-specific information necessary to run
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− | VxWorks for the walnut (IBM PPC405GP) BSP. Before using a board with
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− | VxWorks, verify that the board runs in the factory configuration by using
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− | vendor-supplied ROMs and jumper settings and checking the RS-232
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− | connection. This BSP supports the PowerPC 405GP Rev D and Rev E parts. Rev
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− | B and Rev C support is deprecated; support remains as in original release,
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− | but has not been validated nor upgraded for this release. Rev A parts are
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− | no longer supported with this release.
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− |
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− | Boot ROMs
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− | The IBM 405GP Evaluation Board uses a single VxWorks-supplied AMD Am29F040
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− | ROM (total 512KB). Install the ROM as follows:
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− |
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− | ROM Socket
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− | -----------
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− | - U27
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− |
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− | The BSP supports the NVRAM (Dallas Semiconductor DS1743) on the walnut
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− | board. The boot parameters will be preserved when the system is powered
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− | off.
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− |
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− | Jumpers
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− | Not applicable.
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− |
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− |
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− |
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− | FEATURES
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− |
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− | Supported Features
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− | The following features are supported in this release:
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− | - MMU on the PPC405GP processor (MMU_BASIC only).
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− | - System Timer (uses 405GP PIT hardware timer)
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− | - Auxiliary Timer (uses 405GP FIT hardware timer)
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− | - Watchdog Timer (uses 405GP WDT hardware timer)
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− | - Both 405GP integrated 16550-style serial ports
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− | - 405GP integrated Universal Interrupt Controller (UIC)
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− | - MAL/EMAC (integrated Memory Access Layer and 10/100 Ethernet MAC)
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− | - 405GP PCI controller
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− | - AMD 79C97x family of Ethernet controller (using ln97xEnd driver)
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− | - Allied Telesyn 2450T adapter (AMD 79C970) has been tested
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− | - Allied Telesyn 2700TX adapter (AMD 79C972) has been tested
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− | - other adapters with the same AMD controller may also work.
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− | - SDRAM autoconfiguration (the default 32MB SDRAM DIMM can be replaced
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− | with up to a 128MB DIMM) using IIC to read the DIMM SEEPROM
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− | - ECC SDRAM
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− | - NVRAM (Dallas Semiconductor DS1743)
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− | - Real-time clock (Dallas Semiconductor DS1743) using ds1643rtc.c driver
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− | - JTAG RISCWatch bootrom flash programming tool
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− |
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− |
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− |
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− | HARDWARE DETAILS
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− |
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− | This section documents the details of the device drivers and board hardware
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− | elements.
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− |
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− | Devices
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− | The chip drivers used by this BSP are:
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− | It also provides DCR access routines for the following functional units:
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− | - IBM DMA controller
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− | - IBM external bus controller
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− | - IBM Memory Access Layer (MAL)
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− | - IBM SDRAM controller
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− | - IBM Universal Int Controller (UIC)
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− |
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− | Memory Maps
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− | This BSP supports MMU on the PPC405GP processor. Memory is mapped using a
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− | fixed page size of 4K.
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− |
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− | The sysPhysMemDesc[] array in sysLib.c is used to initialize the Page Table
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− | Entry (PTE) array used by the MMU to translate addresses with single page
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− | (4k) granularity. Address translations for local RAM, memory mapped PCI
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− | bus, memory mapped IO space and local PROM/FLASH are set here. PTEs are
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− | held in a 2-level page table. There is one Level 1 page table and several
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− | Level 2 page tables. The size of the Level 1 table is 4K and the size of
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− | each Level 2 page table is 8K. Each Level 2 table can map up to 4MB of
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− | contiguous memory space.
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− |
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− | Calculating size of page table required
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− | For the following memory map we can calculate the page table size required
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− | as follows:
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− |
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− | Memory Area Address Range Mapped Size Number of Level 2 pages
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− | -------------------------------------------------------------------
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− | Local Memory 0 - Ram size 32MB 8
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− | PCI Memory 0x80000000-0x83FFFFFF 64MB 16
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− | PCI IO Regn 1 0xE8000000-0xE800FFFF 64K 1
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− | PCI IO Regn 2 0xE8800000-0xE88FFFFF 1MB 1
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− | PCI CFG 0xEEC00000-0xEEC00FFF 4K 1
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− | PCI IACK 0xEED00000-0xEED00FFF 4K 0 *
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− | PP Bridge 0xEF400000-0xEF400FFF 4K 1
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− | UART IO Space 0xEF600000-0xEF600FFF 4K 0 *
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− | NVRAM Space 0xF0000000-0xF0001FFF 8K 1
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− | Flash 0xFFF80000-0xFFFFFFFF 512K 1
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− |
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− | * included in previous L2 page
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− |
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− | Total # of L2 pages = 30
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− | Total Memory Required for page table = 30 * 8 + 4 = 244 K.
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− |
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− | By default, to increase performance the instruction MMU (IMMU) is turned
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− | off. In this case, instruction cacheability is controlled by ICCR (which by
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− | default is set to cache all RAM). The IMMU can be re-enabled by defining
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− | USER_I_MMU_ENABLE in config.h.
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− |
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− | Serial Configuration
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− | The default configuration of the serial ports are 9600bps, 8 data bits, no
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− | parity, 1 stop bit.
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− |
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− | Network Configuration
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− | The Enhanced Network Driver (END) used with the integrated EMAC Ethernet
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− | core is "ibmEmacEnd": Note that the boot device name is now "emac", rather
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− | than "ibmEmac". The EMAC works at either 10Mbps or 100Mbps. EMAC gets the
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− | results of the PHY's auto-negotiation process over the MII interface.
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− | board. This controller uses the ln97xEnd driver provided with VxWorks.
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− |
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− | The Ethernet hardware address is configurable at run-time. The first three
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− | bytes of the address are always assumed to be 0x0004AC (IBM) and the last
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− | three bytes are configurable and stored in NVRAM at address 0xF0000500. To
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− | make the ethernet hardware address match the address printed on the decal
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− | attached to the Walnut board use the following example as a guide.
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− |
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− | Ethernet hardware address on the Walnut board decal: 0004AC3E4B22
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− | - boot VxWorks
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− | - execute the following command from the shell:
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− |
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− | sysLanIbmEmacEnetAddrSet 0x00, 0x04, 0xAC, 0x3E, 0x4B, 0x22
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− |
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− | Supported BootRom builds
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− | The following bootrom file types are supported in this release. When using
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− | a Rev B or Rev C processor (which are deprecated), the patch405b.exe or
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− | patch405c.exe tool must be run on the entire ELF file. If a compressed
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− | bootrom is built, this is not possible.
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− |
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− | bootrom_uncmp (405GP Rev B (deprecated), C (deprecated), D, E)
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− | bootrom_uncmp.hex (405GP Rev B (deprecated), C (deprecated), or D, E)
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− | bootrom (405GP Rev D, E only)
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− | bootrom.hex (405GP Rev D, E only)
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− |
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− | ** Note: bootrom builds are only supported through the command line
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− | makefiles -- do not use the project mechanism to build a boot ROM.
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− |
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− | For PPC405GP_REVB (deprecated):
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− |
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− | A batch file has been provided that will post-process the bootrom_uncmp
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− | file. After bootrom_uncmp is built, run the bootrrb.bat file. bootrrb.bat
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− | will modify bootrom_uncmp and will create a new bootrom_uncmp.hex.
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− |
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− | For PPC405GP_REVC (deprecated):
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− |
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− | A batch file has been provided that will post-process the bootrom_uncmp
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− | file. After bootrom_uncmp is built, run the bootrrc.bat file. bootrrc.bat
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− | will modify bootrom_uncmp and will create a new bootrom_uncmp.hex.
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− |
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− | For PPC405GP_REVD_OR_E:
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− |
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− | It is not necessary to post-process the bootrom files when using the 405GP
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− | Rev D or E processor.
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− |
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− | For all processor revisions:
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− |
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− | The standard uncompressed ROM and ROM-resident project configuration are
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− | not supplied because they will not fit in the bootrom.
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− |
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− | Creating a bootrom, and bringing up vxWorks
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− | Create a bootrom by either
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− |
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− | a) Rebuilding bootrom_uncmp.hex image and programming it into an
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− | AMD 29F040 flash part using the following steps:
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− |
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− | - For PPC405GP_REVD_OR_E
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− | - make bootrom_uncmp.hex or bootrom.hex
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− |
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− | b) If you have a JTAG RISCWatch processor probe, you can use
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− | vx_rw_flash.cmd to program the flash part (see below).
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− |
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− | Connect a terminal or terminal emulator to the board (the 9 pin connector
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− | closest to the printed circuit board). Emulator parameters should be set to
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− | 9600bps, 8 data bits, no parity, 1 stop bit. Power-up the board, you should
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− | get an error because the default boot line in config.h is not 100% correct
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− | for your environment. Type in new configuration parameters using the
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− | bootrom menu (set boot device : emac). Your new configuration will be
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− | stored in the NVRAM.
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− |
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− | Workbench bootrom flash programming utility
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− | a) Install the WindRiver ICE and power it on.
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− |
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− | Connect the JTAG interface cable from the Wind River ICE to the
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− | PPC405GP board JTAG connector (J24 located on the CPU card). When all
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− | of the connections have been made, power up the target board and
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− | create a Wind River ICE connection in Workbench.
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− |
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− | b) Configure the Workbench connection.
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− |
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− | When creating the connection, specify the PPC405GP CPU.
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− | Enter the IP address of the Wind River ICE when requested.
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− |
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− | c) Load the proper PPC405GP register setting for WindRiver ICE.
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− |
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− | Once you have connected the probe to the CPU, right-click on the
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− | connection in the target manager and attach to the CPU core. At
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− | this point, you can go to the main Workbench Window tab at the top
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− | of the view and select "show view". Browse the view list and select
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− | OCD Command Shell. This launches the original BKM command shell.
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− | Navigate to the target manager and right-click on core(405GP). Select
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− | the reset tab. You can now put the register file provided by
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− | the installation in "play register file" (for example,
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− | registers/PowerPC/4xx/IBM/405gp.reg). Reset with IN then click the
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− | reset download button. You have now loaded the target board with
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− | enough settings to program the boot ROM. Close the Reset and
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− | Download window after the register file playback finishes.
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− | Select "Window > show view" again and select Flash Programmer.
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− |
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− | d) Converting the bootrom.hex file to bootrom.bin.
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− |
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− | Select the Add/Remove tab in the flash programmer. Click
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− | "convert file" and navigate to the boot loader project you created
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− | previously e.g. WindRiver\workspace\PPC405BootProj\bootrom.hex.
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− | Select the project. The start address should be 0x0 and the end
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− | address should be set to 0xffffffff. Click "convert and add" to convert
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− | the file.
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− | At this point, the file is added to the list. Click on the start
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− | address entry (should be 0x0) and change it to 0xfff80000. The file
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− | is now ready for programming.
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− |
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− | e) Program the PPC405GP flash.
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− |
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− | "Erase/Program".
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− |
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− | Go to OCD command shell and type IN. Be sure this returns the BKM
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− |
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− | RISCWatch bootrom flash programming utility
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− | An IBM RISCWatch based command file (vx_rw_flash.cmd) is provided that will
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− | program bootrom_uncmp.hex into the AMD Am29F040 flash part on the Walnut
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− | board. A RISCWatch JTAG processor probe and RISCWatch software version 4.5
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− | or newer is required to use this utility.
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− |
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− |
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− |
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− | NOTE
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− |
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− | The vx_rw_flash.cmd utility may need modification if you use a different
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− | SDRAM DIMM than was shipped with the Walnut board (see notes inside
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− | vx_rw_flash.cmd).
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− |
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− | To use this utility,
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− | - make bootrom_uncmp via the command line interface (not with the IDE).
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− | - Run the bootrr_.bat batch file for the correct processor revision.
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− | This step will create a patched version of bootrom_uncmp.hex
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− | NOTE: The manual step of adding the branch instruction to
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− | bootrom_uncmp.hex is NOT necessary if using this utility!
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− | - Start IBM JTAG RISCWatch
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− | - Make sure that the RISCWatch search path is set up to find files
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− | in the Walnut BSP directory. One way to do this is to execute the
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− | following RISCWatch command:
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− | srchpath add c:\WR\VxWorks\target\config\walnut
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− | - Execute the following command to start the flash programming process.
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− | This example will place the bootrom_uncmp.hex file into the flash.
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− | exec vx_rw_flash.cmd {"bootrom_uncmp.hex"}
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− |
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− |
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− |
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− | SPECIAL CONSIDERATIONS
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− |
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− | PowerPC 405GP Rev A (PVR = 0x40110000)
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− | This initial hardware sample is no longer supported.
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− |
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− | PowerPC 405GP Rev B (PVR = 0x40110040) errata
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− | There are errata in the 405GP Rev B chip that affect the operation of this
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− | Board Support Package. You should familiarize yourself with them. A current
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− | 405GP errata list is available from the PowerPC Technical support group
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− | (ppcsupp@us.ibm.com). To avoid 405GP Rev B errata a tool patch405b.exe has
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− | been included. This tool searches an ELF executable file (output of the
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− | linker) for certain patterns of instructions related to the above errata.
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− | If it finds a potential problem, it uses reserved space provided by
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− | patchtblb.s to create a "patch" which will avoid the errata. The patch
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− | table is allocated inside of sysALib.s because it includes patchtblb.s.
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− |
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− | If you are using a 405GP Rev B be sure to define PPC405GP_REVB in config.h.
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− |
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− | PowerPC 405GP Rev C (PVR = 0x40110082) errata
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− | There are errata in the 405GP Rev C chip that affect the operation of this
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− | Board Support Package. You should familiarize yourself with them. A current
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− | 405GP errata list is available from the PowerPC Technical support group
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− | (ppcsupp@us.ibm.com). To avoid 405GP Rev C errata a tool patch405c.exe has
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− | been included. This tool searches an ELF executable file (output of the
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− | linker) for certain patterns of instructions related to the above errata.
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− | If it finds a potential problem, it uses reserved space provided by
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− | patchtblc.s to create a "patch" which will avoid the errata. The patch
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− | If you are using a 405GP Rev D be sure to define PPC405GP_REVD_OR_E in
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− | config.h.
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− |
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− | PowerPC 405GP Rev E (PVR = 0x40110145) errata
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− | There are errata in the 405GP Rev E chip that affect the operation of this
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− | Board Support Package. You should familiarize yourself with them. A current
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− | 405GP errata list is available from the PowerPC Technical support group
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− | (ppcsupp@us.ibm.com).
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− |
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− | If you are using a 405GP Rev E be sure to define PPC405GP_REVD_OR_E in
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− | config.h.
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− |
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− | PowerPC 405GPr Rev B (PVR = 0x50910951) errata
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− | There are errata in the 405GPr Rev B chip that affect the operation of this
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− | Board Support Package. You should familiarize yourself with them. A current
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− | 405GPr errata list is available from the PowerPC Technical support group
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− | (ppcsupp@us.ibm.com).
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− |
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− | If you are using a 405GPr Rev B be sure to define PPC405GPR_REVB in
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− | config.h.
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− |
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− |
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− |
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− | BIBLIOGRAPHY
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− |
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− | Please refer to the following documents for further information on the
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− | Walnut board.
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− |
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− | PowerPC 405 Reference Board Manual located at
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− | 405GP_GPR/PPC405GP_EBM2006__v1_00.pdf obtained from http://www.amcc.com
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− | (also on the PowerPC Embedded Processors, Cores, and Tools CDROM)
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− |
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− | 405GP_settings.pdf included in this BSP.
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− |
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− |
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− |
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− | SEE ALSO
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− |
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− | VxWorks Programmer's Guide: Configuration, VxWorks Programmer's Guide:
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− | Architecture Appendix
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− |
| |
− | </pre>
| |
− |
| |
− | == boot format ==
| |
− |
| |
− | === original firmware ===
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− |
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− | netbsd-guide says "Do not use the plain ELF kernel as the file provided to the firmware, use the ``netbsd.img'' file (which is in the format the firmware expects). Of course, you should put the matching ``netbsd'' as /netbsd on your root file system, otherwise some kernel grovellers won't work"
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− |
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− | what is the binary format expected by the original firmware ?
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− |
| |
− | == jtag ==
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− |
| |
− | === ibm/amcc-walnut jtag connector ===
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− |
| |
− | {| border="1" cellspacing="0" cellpadding="5" align="center"
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− | |(01) TDO
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− | |(02) nc
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− | |-
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− | |(03) TDI
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− | |(04) nc
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− | |-
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− | |(05) nc
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− | |(06) 3.3v
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− | |-
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− | |(07) TCK
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− | |(08) nc
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− | |-
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− | |(09) TMS
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− | |(10) nc
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− | |-
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− | |(11) HALT
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− | |(12) nc
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− | |-
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− | |(13) nc
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− | |(14) *NC*
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− | |-
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− | |(15) nc
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− | |(16) gnd
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− | |-
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− | |}
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− |
| |
− | === dht-walnut jtag pinout ===
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− |
| |
− | '''NOTE'''
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− |
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− | * DHT-Walnut: JTAG Pin Out Connector Specifications for DHT-walnut-PPC405GP
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− | * AMCC-PPC4xx: JTAG Pin Out Connector Specifications for AMCC PPC 44X, 40X (4XX) Processors: 405EP, 405GP, 405GPR, 440GP, 440EP, 440GX, 440GR, 440EPX, 440GRX, 440SP, 440SPE
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− |
| |
− |
| |
− | {| border="1" cellspacing="0" cellpadding="5" align="center"
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− | ! pin
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− | ! DHT-WALNUT
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− | ! AMCC-PCC4xx
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− | |-
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− | |01
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− | |TDO
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− | |TDO
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− | |-
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− | |02
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− | |nc
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− | |nc
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− | |-
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− | |03
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− | |TDI
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− | |TDI
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− | |-
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− | |04
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− | |TRST
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− | |TRST
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− | |-
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− | |05
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− | |*NC*<---
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− | |*NC*<---
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− | |-
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− | |06
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− | |Vcc
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− | |Vcc
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− | |-
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− | |07
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− | |TCK
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− | |TCK
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− | |-
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− | |08
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− | |nc
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− | |KSTP_IN
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− | |-
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− | |09
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− | |TMS
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− | |TMS
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− | |-
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− | |10
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− | |nc
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− | |nc
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− | |-
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− | |11
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− | |SRESET
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− | |SRESET
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− | |-
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− | |12
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− | |nc
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− | |nc
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− | |-
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− | |13
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− | |HRESET
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− | |HRESET
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− | |-
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− | |14
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− | |nc
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− | |reserved
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− | |-
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− | |15
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− | |nc
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− | |CKSTP_OUT
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− | |-
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− | |16
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− | |gnd
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− | |gnd
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− | |-
| |
− | |}
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− |
| |
− |
| |
− | '''Pin Out description'''
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− |
| |
− | * TDO=JTAG Test Data Out
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− | * TDI=JTAG Test Data In
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− | * TRST=JTAG Test Reset
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− | * TCK=JTAG Test Clock
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− | * TMS=JTAG Test Mode Select
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− | * *NC*=not connected, used as cable reference
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− | * nc=simply not connected
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− | * SRESET=Soft-Reset
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− | * HRESET=Hard-Reset
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− | * KSTP_OUT=?
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− | * CKSTP_IN=?
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− | * Vcc=board ref voltage, 3V
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− |
| |
− |
| |
− | == firmware replacing ==
| |
− |
| |
− | see dht-walnut "recover from a breakage" ... using that procedure you will be able to replace the ibm/amcc-walnut original firmware with uboot
| |
− |
| |
− | === download ===
| |
− |
| |
− | [[Media:ibm-walnut-uboot.tgz|ibm-walnut-uboot.tgz]]
| |