Difference between revisions of "Minnowboard:MinnowMaxCoreboot"

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| style="background-color: #E8E8E8;" width="100%" | <br/><br/><span style="color: red;">'''NOTICE:'''</span> This page is no longer being actively maintained here.  Please refer to [http://wiki.minnowboard.org/Coreboot http://wiki.minnowboard.org/Coreboot] for the latest information.<br/><br/><br/>
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This page gives a step by step guide to building coreboot for the Minnowboard Max.
 
This page gives a step by step guide to building coreboot for the Minnowboard Max.
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__toc__
  
 
= Requirements =
 
= Requirements =

Latest revision as of 11:34, 5 November 2015



NOTICE: This page is no longer being actively maintained here. Please refer to http://wiki.minnowboard.org/Coreboot for the latest information.


This page gives a step by step guide to building coreboot for the Minnowboard Max.

Requirements

  • gcc
  • g++
  • git
  • make
  • ncurses-dev
  • flex
  • bison

Get sources and tools

NOTE: for simplicity, put all downloads and items extracted into the same directory.

Coreboot

git clone http://review.coreboot.org/p/coreboot
cd coreboot
git submodule update --init --checkout
git checkout 7effaa4c02d974b59bd86307a54cefb7bb046a3a

Intel Firmware Support Package (FSP)

Setup

TXE and SPI descriptor

First build a coreboot utility called ifdtool that's located within the coreboot directory

cd coreboot/util/ifdtool
make
cd ../../../

Download the original firmware binary here

unzip -d maxfirmware MinnowBoard.MAX_.X64.078.R02.bin_.zip
cd maxfirmware

Run ifdtool to extract the TXE and SPI descriptor from the firmware image

../coreboot/util/ifdtool/ifdtool -x MinnowBoard.MAX.X64.078.R02.bin

You should now have 4 files starting with flashregion_ Link flashregion_0_flashdescriptor.bin to descriptor.bin

ln -s flashregion_0_flashdescriptor.bin descriptor.bin

Link flashregion_1_bios.bin to txe.bin

ln -s flashregion_1_bios.bin txe.bin
  • Ignore the other two flashregion files as they won't be used

Coreboot

cd coreboot
  • in src/soc/intel/fsp_baytrail/Kconfig line 75, change default value of SMM_TSEG_SIZE from '0x100000' to '0x800000'
make menuconfig
  • load provided config
  • save config to .config
  • If you have a single core Minnowboard Max, change "Mainboard" -> "Memory SKU to build" to 1GB

Building

make crossgcc-x64 crossgcc-i386
make
  • The firmware produced is build/coreboot.rom

Building without TXE/SPI descriptor

make menuconfig
  • Set Chipset -> Include the TXE to No
make crossgcc-x64 crossgcc-i386
make
  • When flashing the firmware, only flash the last 3MB of the 8 MB image onto the last 3MB of the chip
    • Example command using flashrom and a dediprog: echo 00500000:007fffff coreboot > regions.txt ; sudo flashrom -p dediprog -l regions.txt -i coreboot -w coreboot.rom
  • If you accidentally overwrite the first half, you will need to reflash the original firmware, which is available here.