Difference between revisions of "Minnowboard:MinnowMaxCoreboot"

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(Added quick coreboot building instructions for the Minnowboard Max)
 
(Add "Building without TXE/SPI descriptor" section)
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This page gives a step by step guide to building coreboot for the Minnowboard Max.
 
This page gives a step by step guide to building coreboot for the Minnowboard Max.
 
Note that these instructions assume you have the TXE and spi descriptor, which are not yet publicly available.
 
  
 
= Requirements =
 
= Requirements =
Line 31: Line 29:
 
=== TXE and SPI descriptor ===
 
=== TXE and SPI descriptor ===
 
* ???????
 
* ???????
* Not yet available. See [[Minnowboard:MinnowMaxCoreboot#Building without TXE/SPI descriptor|Building without TXE/SPI descriptor]] section below.
+
* Not yet available. See [[Minnowboard:MinnowMaxCoreboot#Building without TXE/SPI descriptor|Building without TXE/SPI descriptor]] section below for a possible workaround.
  
 
= Setup =
 
= Setup =
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** If you have a single core Minnowboard Max, change minnowmax_2gb.absf to minnowmax_1gb.absf
 
** If you have a single core Minnowboard Max, change minnowmax_2gb.absf to minnowmax_1gb.absf
 
** DO NOT USE THE GUI. THE GUI DOES NOT WORK ON ALL LINUX DISTROS AND IS NOT NECESSARY FOR THIS.
 
** DO NOT USE THE GUI. THE GUI DOES NOT WORK ON ALL LINUX DISTROS AND IS NOT NECESSARY FOR THIS.
 +
* cd ..
  
 
=== Coreboot ===
 
=== Coreboot ===
 +
* cd coreboot
 
* in src/soc/intel/fsp_baytrail/Kconfig line 127, change 'string' to 'string "ME PATH"'
 
* in src/soc/intel/fsp_baytrail/Kconfig line 127, change 'string' to 'string "ME PATH"'
 
* make menuconfig
 
* make menuconfig
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= Building =
 
= Building =
* cd coreboot
 
 
* make crossgcc
 
* make crossgcc
 
* make
 
* make
 +
 +
= Building without TXE/SPI descriptor =
 +
This section has not been tested, but should work.
 +
* make menuconfig
 +
** Set Chipset -> Include the TXE to No
 +
** Set Mainboard -> ROM chip size to 4 MB
 +
* make crossgcc
 +
* make
 +
* When flashing the firmware, put the 4 MB image on the second half of the 8 MB chip, being careful not to overwrite the first half.

Revision as of 16:41, 4 December 2014

This page gives a step by step guide to building coreboot for the Minnowboard Max.

Requirements

  • gcc
  • git
  • make
  • ncurses-dev

Get sources and tools

NOTE: for simplicity, put all downloads and items extracted into the same directory.

Coreboot

FSP

  • Download FSP archive
  • extract from archive
  • follow instructions in Readme_Extract to extract FSP

Binary Configuration Tool

  • Download BCT archive
  • extract archive from archive
  • extract from archive

TXE and SPI descriptor

Setup

FSP

  • cd bct
  • ./bct --bin ../BAY_TRAIL_FSP_KIT/FSP/BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd --absf ../coreboot/src/vendorcode/intel/fsp/baytrail/absf/minnowmax_2gb.absf --bout ../minnowboard-max.fsp
    • If you have a single core Minnowboard Max, change minnowmax_2gb.absf to minnowmax_1gb.absf
    • DO NOT USE THE GUI. THE GUI DOES NOT WORK ON ALL LINUX DISTROS AND IS NOT NECESSARY FOR THIS.
  • cd ..

Coreboot

  • cd coreboot
  • in src/soc/intel/fsp_baytrail/Kconfig line 127, change 'string' to 'string "ME PATH"'
  • make menuconfig
  • load provided config
  • save config to .config
  • If you have a single core Minnowboard Max, change "Mainboard" -> "Memory SKU to build" to 1GB
  • Set "Chipset" -> "ME PATH" to the directory containing TXE and SPI descriptor

Building

  • make crossgcc
  • make

Building without TXE/SPI descriptor

This section has not been tested, but should work.

  • make menuconfig
    • Set Chipset -> Include the TXE to No
    • Set Mainboard -> ROM chip size to 4 MB
  • make crossgcc
  • make
  • When flashing the firmware, put the 4 MB image on the second half of the 8 MB chip, being careful not to overwrite the first half.