Difference between revisions of "Minnowboard:MinnowMaxCoreboot"
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= Building without TXE/SPI descriptor = | = Building without TXE/SPI descriptor = | ||
− | |||
* make menuconfig | * make menuconfig | ||
** Set Chipset -> Include the TXE to No | ** Set Chipset -> Include the TXE to No | ||
− | |||
* make crossgcc | * make crossgcc | ||
* make | * make | ||
− | * When flashing the firmware, | + | * When flashing the firmware, only flash the last 3MB of the 8 MB image onto the last 3MB of the chip |
+ | ** Example command using flashrom and a dediprog: echo 00500000:007fffff coreboot > regions.txt ; sudo flashrom -p dediprog -l regions.txt -i coreboot -w coreboot.rom | ||
* If you accidentally overwrite the first half, you will need to reflash the original firmware, which is available [https://uefidk.com/content/minnowboard-max here]. | * If you accidentally overwrite the first half, you will need to reflash the original firmware, which is available [https://uefidk.com/content/minnowboard-max here]. |
Revision as of 16:34, 17 December 2014
This page gives a step by step guide to building coreboot for the Minnowboard Max.
Contents
Requirements
- gcc
- git
- make
- ncurses-dev
Get sources and tools
NOTE: for simplicity, put all downloads and items extracted into the same directory.
Coreboot
- git clone http://review.coreboot.org/p/coreboot
- cd coreboot
- git submodule update --init --checkout
- git checkout b9a0809faeeef67e46cda17cf8f7a839c6fe614c
- Download config
FSP
- Download FSP archive
- extract from archive
- follow instructions in Readme_Extract to extract FSP
Binary Configuration Tool
- Download BCT archive
- extract archive from archive
- extract from archive
TXE and SPI descriptor
- ???????
- Not yet available. See Building without TXE/SPI descriptor section below for a possible workaround.
Setup
FSP
- cd bct
- ./bct --bin ../BAY_TRAIL_FSP_KIT/FSP/BAYTRAIL_FSP_GOLD_002_10-JANUARY-2014.fd --absf ../coreboot/src/vendorcode/intel/fsp/baytrail/absf/minnowmax_2gb.absf --bout ../minnowboard-max.fsp
- If you have a single core Minnowboard Max, change minnowmax_2gb.absf to minnowmax_1gb.absf
- DO NOT USE THE GUI. THE GUI DOES NOT WORK ON ALL LINUX DISTROS AND IS NOT NECESSARY FOR THIS.
- cd ..
Coreboot
- cd coreboot
- in src/soc/intel/fsp_baytrail/Kconfig line 127, change 'string' to 'string "ME PATH"'
- make menuconfig
- load provided config
- save config to .config
- If you have a single core Minnowboard Max, change "Mainboard" -> "Memory SKU to build" to 1GB
- Set "Chipset" -> "ME PATH" to the directory containing TXE and SPI descriptor
Building
- make crossgcc
- make
- The firmware produced is build/coreboot.rom
Building without TXE/SPI descriptor
- make menuconfig
- Set Chipset -> Include the TXE to No
- make crossgcc
- make
- When flashing the firmware, only flash the last 3MB of the 8 MB image onto the last 3MB of the chip
- Example command using flashrom and a dediprog: echo 00500000:007fffff coreboot > regions.txt ; sudo flashrom -p dediprog -l regions.txt -i coreboot -w coreboot.rom
- If you accidentally overwrite the first half, you will need to reflash the original firmware, which is available here.