Parallella Hardware
Revision as of 10:09, 9 April 2013 by Carrierdetect (talk | contribs) (Created page with "Category: Parallella '''This page is presently a stub — please bear with us as it is filled out.''' ~~~~ ==Introduction== ''To follow.'' ==Prototypes== ''To follow...")
This page is presently a stub — please bear with us as it is filled out. Carrierdetect (talk) 17:09, 9 April 2013 (UTC)
Introduction
To follow.
Prototypes
To follow.
Specifications
Please note that these are preliminary specifications and subject to change.
| 18-core | 66-core | |
|---|---|---|
| Target price: | US$99 | US$TBC |
| System-on-a-chip (SoC): | Zynq 7010 (Host + FPGA) | |
| CPU: | 800 MHz Dual ARM® Cortex™-A9 MPCore™ with CoreSight™ | |
| Many-core accelerator: | Epiphany-III 16-core 65nm Microprocessor with 32 GFLOPS peak performance (E16G301) | Epiphany-IV 64-core 28nm Microprocessor with 100 GFLOPS peak performance (E64G401) |
| Memory (SDRAM) | 1024 MiB DDR3L | |
| USB 2.0 ports: | 1x USB 2.0 | 1x USB 2.0 OTG | |
| Video outputs: | Micro HDMI | |
| Audio outputs: | Single bit SPDIF on the PEC_POWER connector | |
| Audio inputs: | none, but a USB mic or sound-card could be added | |
| Onboard Storage: | 32Mb QSPI Flash Memory | MicroSD | |
| Onboard Network: | 10/100/1000 wired Ethernet RJ45 | |
| PEC_POWER expansion: | 1V, 1.35V, 1.8V, 3.3V & 5V power supplies. I2C, UART, SPDIF, JTAG | |
| PEC_FPGA expansion: | includes 48 bidirectional signals that can be configured within the Zynq device to support a number of different signal standards. When configured as LVDS signals, each differential signal pair provides a maximum bandwidth of 950Mbps. In aggregate, the PEC_FPGA connections can provide 22Gbps of total I/O bandwidth. | |
| PEC_NORTH/PEC_SOUTH expansion: | 3.2GB/s total I/O bandwidth via 2.5V LVDS | 2.8GB/s total I/O bandwidth via 1.8V subLVDS |
| Real-time clock: | None | |
| Power source: | 5 V (DC) at 1A | |
| Size: | 3.4" x 2.15" | |
