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From Talk:Embedded Open Modular Architecture/EOMA68
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| Time | User | Activity | Comment |
|---|---|---|---|
| 08:57, 31 July 2016 | Lkcl (talk | contribs) | New reply created |
(Reply to Requirements for SD/MMC and SPI) |
| 05:59, 31 July 2016 | Rsaxvc (talk | contribs) | New thread created |
"In essence, the SD/MMC committee have caused a bit of trouble, here, but it may be best to trust their experience in that SD/MMC Cards have probably not, for some considerable time, been actually using SPI mode, but have been offering the 2, 4 (and now 8) lane capability for a long, long time."
By 2-bit, do we mean the SD/MMC mode where data is transferred one bit at a time over either command or data lines? Just to get the terminology right, I believe SD calls it 1-bit SD.
